Abstract: Technologies for a high gradient of dopant concentration in gate-all-around transistors are disclosed. In an illustrative embodiment, a source/drain region of a gate-all-around transistor may have a relatively high dopant concentration, such as a dopant concentration of over 1020 cm?3, and an adjacent channel region may have a relatively low dopant concentration, such as a dopant concentration of less than 1018 cm?3. At an interface between the source/drain region and the channel region, the logarithmic slope of the dopant concentration may be high, such as two orders of magnitude in less than a nanometer. In order to maintain such a high dopant concentration, the source/drain region with a high dopant concentration is deposited using a low-temperature deposition technique after high-temperature processing steps are completed.

Abstract: Semiconductor devices and systems with arsenic-doped sources and drains that include phosphorus-doped contact regions, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes an epitaxial structure and a conductive contact. The epitaxial structure includes silicon, arsenic, and phosphorus, where phosphorus is concentrated in a contact region of the epitaxial structure. The conductive contact is coupled to the contact region of the epitaxial structure, and the conductive contact includes metal.