Patents by Inventor Ethan Schuchman
Ethan Schuchman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10877765Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.Type: GrantFiled: March 10, 2015Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Sebastian Winkel, Ethan Schuchman, Rainer Theuer, Gregor Stellpflug, Tyler N. Sondag
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Patent number: 10437590Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.Type: GrantFiled: September 28, 2017Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Sofia Pediaditaki, Ethan Schuchman, Rangeen Basu Roy Chowdhury, Manjunath Shevgoor
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Patent number: 10409763Abstract: Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.Type: GrantFiled: June 30, 2014Date of Patent: September 10, 2019Assignee: INTEL CORPORATIONInventors: Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Polychronis Xekalakis, Joshua B. Fryman, Allan D. Knies, Naveen Neelakantam, Gregor Stellpflug, John H. Kelm, Mirem Hyuseinova Seidahmedova, Demos Pavlou, Jaroslaw Topp
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Patent number: 10324724Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.Type: GrantFiled: December 16, 2015Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Patrick P. Lai, Tyler N. Sondag, Sebastian Winkel, Polychronis Xekalakis, Ethan Schuchman, Jayesh Iyer
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Publication number: 20190171461Abstract: A processor including a binary translator circuit to convert an instruction stream into an annotated instruction stream comprising an independent code tag identifying an independent code segment and a dependent code tag identifying a dependent code segment, a front end circuit to receive the annotated instruction stream in order, responsive to identifying the independent code tag in the annotated instruction stream, allocate instructions of the independent code segment associated with the independent code tag into a buffer, and responsive to identifying the dependent code tag, reserve a space for the dependent code segment associated with the dependent code tag, and an instruction execution circuit to execute the independent code segment prior to executing the dependent code segment.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Inventors: Kimishkumar Patel, Ethan Schuchman
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Publication number: 20190095203Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Sofia Pediaditaki, Ethan Schuchman, Rangeen Basu Roy Chowdhury, Manjunath Shevgoor
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Patent number: 10055256Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.Type: GrantFiled: February 29, 2016Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Sebastian Winkel, Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian
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Patent number: 9996356Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.Type: GrantFiled: December 26, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Vineeth Mekkat, Oleg Margulis, Jason M. Agron, Ethan Schuchman, Sebastian Winkel, Youfeng Wu, Gisle Dankel
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Patent number: 9858057Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.Type: GrantFiled: December 2, 2015Date of Patent: January 2, 2018Assignee: Intel CorporationInventors: Girish Venkatasubramanian, Chaitanya Mangla, Gerolf F. Hoflehner, Ethan Schuchman
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Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform
Patent number: 9710389Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.Type: GrantFiled: March 10, 2015Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Oleg Margulis, Sumit Ahuja, Polychronis Xekalakis, Yongjun Park, Vineeth Mekkat, Igor Yanover, Sebastian Winkel, Ethan Schuchman -
Publication number: 20170185404Abstract: Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Vineeth Mekkat, Oleg Margulis, Jason M. Agron, Ethan Schuchman, Sebastian Winkel, Youfeng Wu, Gisle Dankel
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Publication number: 20170177343Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Inventors: Patrick P. Lai, Tyler N. Sondag, Sebastian Winkel, Polychronis Xekalakis, Ethan Schuchman, Jayesh Iyer
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Patent number: 9600283Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.Type: GrantFiled: September 15, 2015Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Ethan Schuchman, Hong Wang, Chris Weaver, Belliappa M. Kuttanna, Asit Mallick, Vivek K. De, Per Hammarlund
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Patent number: 9460022Abstract: A mechanism is described for facilitating dynamic and efficient binary translation-based translation lookaside buffer prefetching according to one embodiment. A method of embodiments, as described herein, includes translating code blocks into code translation blocks at a computing device. The code translation blocks are submitted for execution. The method may further include tracking, in runtime, dynamic system behavior of the code translation blocks, and inferring translation lookaside buffer (TLB) prefetching based on the analysis of the tracked dynamic system behavior.Type: GrantFiled: March 15, 2013Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Girish Venkatasubramanian, Ethan Schuchman
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Publication number: 20160283247Abstract: Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.Type: ApplicationFiled: March 25, 2015Publication date: September 29, 2016Inventors: Girish Venkatasubramanian, Ethan Schuchman, David Keppel, Sebastian Winkel, David N. Mackintosh, Jaroslaw Topp
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Publication number: 20160274944Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.Type: ApplicationFiled: February 29, 2016Publication date: September 22, 2016Inventors: Sebastian Winkel, Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian
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Publication number: 20160266905Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.Type: ApplicationFiled: March 10, 2015Publication date: September 15, 2016Inventors: Sebastian Winkel, Ethan Schuchman, Rainer Theuer, Gregor Stellpflug, Tyler N. Sondag
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METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORDER INSTRUCTION EXECUTION PLATFORM
Publication number: 20160267009Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.Type: ApplicationFiled: March 10, 2015Publication date: September 15, 2016Inventors: Oleg Margulis, Sumit Ahuja, Polychronis Xekalakis, Yongjun Park, Vineeth Mekkat, Igor Yanover, Sebastian Winkel, Ethan Schuchman -
Publication number: 20160179542Abstract: In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible instruction sequences include a sequence of increment, compare, and jump instructions. In one embodiment, a processing device provides support for the fused macroinstruction. In one embodiment, the processing device executes the fused macroinstruction within a single execution stage of a processor pipeline. In one embodiment, the fused macroinstruction is performed within a single execution cycle.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Patrick P. Lai, Tyler N. Sondag, Sebastian Winkel, Polychronis Xekalakis, Ethan Schuchman
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Publication number: 20160085556Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Sebastian Winkel, Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian