Abstract: Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

Abstract: Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS).Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage.In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands.

Abstract: A shared time-of-day (TOD) clock modification bit is used in a multiprocessing system in which the timing facilities in two or more CPUs are implemented as a function of a single TOD clock. This bit helps avoid timer errors that occur as the result of one central processing unit (CPU) changing the TOD clock value while another CPU is executing an instruction which determines a CPU timer value. Whenever the microcode in any one of the CPUs reads the TOD clock, it obtains the Shared TOD Clock Modification Bit in addition to the TOD value. This bit indicates if the TOD clock read operation just completed is the first such operation executed by that CPU since the TOD clock was updated by another CPU sharing the same TOD clock. If it is, certain instructions take action to correct timer errors introduced by the change in the TOD clock value.