Patents by Inventor Etienne Cesar

Etienne Cesar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LEVEL CONVERTER CIRCUIT
    Publication number: 20230378957
    Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventor: Etienne Cesar
  • Level converter circuit
    Patent number: 11757448
    Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: September 12, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Etienne Cesar
  • LEVEL CONVERTER CIRCUIT
    Publication number: 20220045665
    Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.
    Type: Application
    Filed: July 22, 2021
    Publication date: February 10, 2022
    Inventor: Etienne Cesar
  • Clock synchronization device
    Patent number: 10530563
    Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS (GRENOBLE2) SAS
    Inventor: Etienne Cesar
  • Clock Synchronization Device
    Publication number: 20180375637
    Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
    Type: Application
    Filed: February 19, 2018
    Publication date: December 27, 2018
    Inventor: Etienne Cesar