Patents by Inventor Etienne Eustache

Etienne Eustache has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor
    Patent number: 11515394
    Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 29, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Etienne Eustache, Bassem Salem, Jean-Michel Hartmann, Franck Bassani, Mohamed-Aymen Mahjoub
  • METHOD FOR THE NANOSCALE ETCHING OF A GERMANIUM-TIN ALLOY (GeSn) FOR A FET TRANSISTOR
    Publication number: 20210242313
    Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.
    Type: Application
    Filed: January 22, 2021
    Publication date: August 5, 2021
    Inventors: Etienne EUSTACHE, Bassem SALEM, Jean-Michel HARTMANN, Franck BASSANI, Mohamed-Aymen MAHJOUB
  • Microstructured substrate
    Patent number: 10355302
    Abstract: A microstructured substrate includes a plurality of at least one elementary microstructure. An electrical storage device, and more particularly an all-solid-state battery, can include the microstructured substrate.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 16, 2019
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE DE NANTES
    Inventors: Christophe Lethien, Pascal Tilmant, Etienne Eustache, Nathalie Rolland, Thierry Brousse
  • MICROSTRUCTURED SUBSTRATE
    Publication number: 20160240882
    Abstract: A microstructured substrate includes a plurality of at least one elementary microstructure. An electrical storage device, and more particularly an all-solid-state battery, can include the microstructured substrate.
    Type: Application
    Filed: October 2, 2014
    Publication date: August 18, 2016
    Inventors: Christophe Lethien, Pascal Tilmant, Etienne Eustache, Nathalie Rolland, Thierry Brousse