Abstract: A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.