Abstract: A 3D face model is generated by calculating depths on a left image and a right image. An eye-distance of a user is determined according to the 3D face model. A precise stereoscopic digital image of the user is generated by integrating the 3D face model, the eye-distance, and a user digital image processed by human-body rendering and face morphing. The stereoscopic digital image generated by following the user's appearance can be utilized by the user to serve as an avatar, for enhancing entertainments of the user when the user plays an interactive game using the avatar with other players on the Internet.

Abstract: A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is coupled to the super speed circuit and the non-super speed circuit for controlling the super speed circuit or the non-super speed circuit to transmit data with a USB peripheral device, and turning-on or turning-off of the super speed circuit and the non-super speed circuit.

Abstract: A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Abstract: A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line.

Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Abstract: A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length.

Abstract: A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal.