Patents by Inventor Etsuko Arakawa

Etsuko Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7564139
    Abstract: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The term “an integrated circuit film” means a film-like integrated circuit which is manufactured based on an integrated circuit manufactured by a semiconductor film formed over a substrate such as a glass substrate or a quartz substrate. In the present invention, the integrated circuit film is manufactured by a technique for transferring.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: July 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Etsuko Arakawa, Shunpei Yamazaki
  • Publication number: 20080088034
    Abstract: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The term “an integrated circuit film” means a film-like integrated circuit which is manufactured based on an integrated circuit manufactured by a semiconductor film formed over a substrate such as a glass substrate or a quartz substrate. In the present invention, the integrated circuit film is manufactured by a technique for transferring.
    Type: Application
    Filed: November 30, 2007
    Publication date: April 17, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideaki Kuwabara, Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Etsuko Arakawa, Shunpei Yamazaki
  • Patent number: 7335593
    Abstract: A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Arakawa, Kiyoshi Kato, Yoshiyuki Kurokawa
  • Patent number: 7303942
    Abstract: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The term “an integrated circuit film” means a film-like integrated circuit which is manufactured based on an integrated circuit manufactured by a semiconductor film formed over a substrate such as a glass substrate or a quartz substrate. In the present invention, the integrated circuit film is manufactured by a technique for transferring.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: December 4, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Etsuko Arakawa, Shunpei Yamazaki
  • Publication number: 20050164434
    Abstract: A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.
    Type: Application
    Filed: March 24, 2005
    Publication date: July 28, 2005
    Inventors: Etsuko Arakawa, Kiyoshi Kato, Yoshiyuki Kurokawa
  • Patent number: 6872658
    Abstract: A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 29, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Arakawa, Kiyoshi Kato, Yoshiyuki Kurokawa
  • Publication number: 20040124542
    Abstract: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The term “an integrated circuit film” means a film-like integrated circuit which is manufactured based on an integrated circuit manufactured by a semiconductor film formed over a substrate such as a glass substrate or a quartz substrate. In the present invention, the integrated circuit film is manufactured by a technique for transferring.
    Type: Application
    Filed: December 16, 2003
    Publication date: July 1, 2004
    Inventors: Hideaki Kuwabara, Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Etsuko Arakawa, Shunpei Yamazaki
  • Publication number: 20030104659
    Abstract: A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.
    Type: Application
    Filed: November 22, 2002
    Publication date: June 5, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Etsuko Arakawa, Kiyoshi Kato, Yoshiyuki Kurokawa