Patents by Inventor Etsuko KAMATA

Etsuko KAMATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220414499
    Abstract: A property prediction system for a semiconductor element is provided. The property prediction system includes a memory unit, an input unit, a processing unit, and an arithmetic unit. The processing unit has a function of creating a learning data set from first data stored in the memory unit, a function of creating prediction data from second data supplied from the input unit, a function of converting qualitative data (a material name or a compositional formula) into quantitative data (the properties of an element and a composition), and a function of performing extraction or removal on the first data and the second data. The first data includes step lists of first to m-th semiconductor elements (m is an integer of 2 or more) and the properties of the first to m-th semiconductor elements. The second data includes a step list of an (m+1)-th semiconductor element.
    Type: Application
    Filed: November 6, 2020
    Publication date: December 29, 2022
    Inventors: Shunsuke HOSOUMI, Kunihiko SUZUKI, Kanta ABE, Yuji IWAKI, Daigo SHIMADA, Etsuko KAMATA
  • Patent number: 11257722
    Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki Tanemura, Etsuko Kamata, Hiromi Sawai, Daisuke Matsubayashi
  • Publication number: 20210090961
    Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.
    Type: Application
    Filed: July 18, 2018
    Publication date: March 25, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuki TANEMURA, Etsuko KAMATA, Hiromi SAWAI, Daisuke MATSUBAYASHI
  • Patent number: 10615187
    Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinpei Matsuda, Daigo Ito, Daisuke Matsubayashi, Yasutaka Suzuki, Etsuko Kamata, Yutaka Shionoiri, Shuhei Nagatsuka
  • Publication number: 20180033807
    Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Inventors: Shinpei MATSUDA, Daigo ITO, Daisuke MATSUBAYASHI, Yasutaka SUZUKI, Etsuko KAMATA, Yutaka SHIONOIRI, Shuhei NAGATSUKA