Patents by Inventor Etsuko TOMITA

Etsuko TOMITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10749001
    Abstract: A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takayuki Hirose, Yutaka Terao, Aki Takigawa, Etsuko Tomita
  • Publication number: 20190172912
    Abstract: A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takayuki HIROSE, Yutaka TERAO, Aki TAKIGAWA, Etsuko TOMITA