Patents by Inventor Etsuo Fukuda
Etsuo Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887845Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: GrantFiled: September 29, 2021Date of Patent: January 30, 2024Assignees: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITYInventors: Kazutaka Kamijo, Etsuo Fukuda, Takashi Ishikawa, Koji Izunome, Moriya Miyashita, Takao Sakamoto, Tetsuo Endoh
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Publication number: 20230243062Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.Type: ApplicationFiled: June 14, 2021Publication date: August 3, 2023Inventors: Haruo SUDO, Takashi ISHIKAWA, Koji IZUNOME, Hisashi MATSUMURA, Tatsuhiko AOKI, Shoji IKEDA, Tetsuo ENDOH, Etsuo FUKUDA
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Publication number: 20230154532Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.Type: ApplicationFiled: November 17, 2022Publication date: May 18, 2023Inventors: Hiroshi YOSHIDA, Toshimasa NAMEKAWA, Satoru ARAKI, Etsuo FUKUDA, Tetsuo ENDOH
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Publication number: 20220093396Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: ApplicationFiled: September 29, 2021Publication date: March 24, 2022Applicants: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITYInventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
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Publication number: 20200211840Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: ApplicationFiled: July 17, 2018Publication date: July 2, 2020Applicants: GlobalWafers Japan Co., Ltd., TOHOKU UNIVERSITYInventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
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Patent number: 6853870Abstract: A semiconductor processing process control system comprising a skip judgment request receiving section for receiving a request for judgment as to whether a process can be skipped or not. A skip judgment yes/no section searches for a judgment plug-in corresponding to the process to be skipped and a judgment execute section activates the judgment plug-in to make a judgment as to whether the process can be skipped or not on the basis of skip judgment logic in the plug-in. A skip execute section effects skipping of the process if the judgment determines that the process can be skipped.Type: GrantFiled: April 2, 2004Date of Patent: February 8, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Shoichi Harakawa, Makoto Ikeda, Etsuo Fukuda
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Publication number: 20040186610Abstract: A semiconductor processing process control system includes a process controller main body (100) for controlling processes for semiconductor processing independently from semiconductor processing devices and contents of intended processing, and a control variable computation programs (210) for obtaining control conditions for semiconductor processing adaptive to semiconductor processing devices and contents of intended processing. The control variable computation programs (210) are used by plugging necessary one of them into the process controller main body (100). When there is any change in semiconductor processing device and content of processing, the system can cope with such changes by merely modifying the control variable computation programs (210). Therefore, the system flexibly, quickly copes with changes in process for processing, computing method of control variables and processing device.Type: ApplicationFiled: April 2, 2004Publication date: September 23, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Shoichi Harakawa, Makoto Ikeda, Etsuo Fukuda
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Patent number: 6745094Abstract: A semiconductor processing process control system includes a process controller main body (100) for controlling processes for semiconductor processing independently from semiconductor processing devices and contents of intended processing, and a control variable computation programs (210) for obtaining control conditions for semiconductor processing adaptive to semiconductor processing devices and contents of intended processing. The control variable computation programs (210) are used by plugging necessary one of them into the process controller main body (100). When there is any change in semiconductor processing device and content of processing, the system can cope with such changes by merely modifying the control variable computation programs (210). Therefore, the system flexibly, quickly copes with changes in process for processing, computing method of control variables and processing device.Type: GrantFiled: June 29, 2000Date of Patent: June 1, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Shoichi Harakawa, Makoto Ikeda, Etsuo Fukuda
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Patent number: 6546300Abstract: A production/manufacturing planning system is provided with a production planning planner 10 and a manufacturing planning scheduler 12. The production planning planner 10 makes the production planning for the whole factory, and the manufacturing planing sheduler 12 makes the manufacturing planning schedule for each of manufacturing lines on the basis of the production planning for the whole factory. Thus, it is possible to more precisely make the production planning and manufacturing planning than that in conventional systems.Type: GrantFiled: December 6, 1999Date of Patent: April 8, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Etsuo Fukuda, Shinichi Hohkibara
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Patent number: 6463350Abstract: A production system has a plurality of production apparatuses, a conveyer which conveys to each production apparatus at each lot, a lot management computer which controls the degree of progress of the production process in each lot, apparatus management computers which control each of production apparatuses, and an intensive management computer which detects the degree of progress of the production process in each lot and operating state of each production apparatus. User interface sections are connected to the apparatus management computer and the intensive management computer, respectively. The user interface sections comprise display apparatuses, respectively. In the screen of the display apparatuses, operating state of each production apparatus and the degree of progress of the production process of the lot in each production apparatus are displayed.Type: GrantFiled: May 26, 1998Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Etsuo Fukuda, Hiroshi Nanami, Hidehiro Okutani
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Patent number: 6438436Abstract: A production scheduling management system includes: a long-range production scheduling unit that receives long-range production scheduling information including at least information on a delivery date of each lot, produces a lot processing schedule based on the delivery date of each lot, and outputs a long-range production schedule; a short-range production scheduling unit that receives the long-range production schedule and short-range production scheduling information, produces a short-range schedule of lot processing so as to fulfill the long-range production schedule, and outputs a short-range production schedule; and a work scheduling unit that receives the short-range production schedule and work scheduling information, produces a work schedule so as to fulfill the short-range production schedule, while taking account of conditions of each machine and conditions of each lot, and generates work schedule.Type: GrantFiled: February 16, 1999Date of Patent: August 20, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Hohkibara, Etsuo Fukuda, Hiroshi Nanami
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Publication number: 20020013632Abstract: A production system comprises a plurality of production apparatuses 1, a conveyer 2 which conveys to each production apparatus 1 at each lot, a lot management computer 3 which controls the degree of progress of the production process in each lot, apparatus management computers 4 which control each production apparatuses 1, and an intensive management computer 5 which detect the degree of progress of the production process in each lot and operating state of each production apparatus 1. User interface sections 6 and 7 are connected to the apparatus management computer 4 and the intensive management computer 5, respectively. The user interface sections 6 and 7 comprise display apparatuses, respectively. In the screen of the display apparatuses 7a, operating state of each production apparatus and the degree of progress of the production process of the lot in each production apparatus are displayed.Type: ApplicationFiled: May 26, 1998Publication date: January 31, 2002Inventors: ETSUO FUKUDA, HIROSHI NANAMI, HIDEHIRO OKUTANI
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Patent number: 6112130Abstract: A process flow, in which wafer processing conditions are described for forming a semiconductor through a plurality of processes, is formed for each lot in one type. A wafer processing is formed for each lot in one type of semiconductor in accordance with the process flow. When a different processing condition should be described according to a wafer in the lot in a certain process of the process flow, the process flow forming includes forming a plurality of different flows in that process by defining division/combination locations from a parent flow. When a faulty processing occurs in the wafer processing in a certain process, the process flow associated with that process is reformed, and a reprocessing is performed in accordance with the reformed process flow.Type: GrantFiled: October 1, 1997Date of Patent: August 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Etsuo Fukuda, Hidehiro Okutani
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Patent number: 5694325Abstract: A system for automatically producing semiconductor products has a section for preparing a process flow containing a series of processes and process conditions for producing different semiconductor products in different quantities in a production line; a section for simulating the producing of semiconductor products according to the process flow; a section for feeding a result of the simulation back to the process flow preparation section, which optimizes the process flow according to the simulation result; and a section for producing semiconductor products according to the optimized process flow.Type: GrantFiled: November 22, 1995Date of Patent: December 2, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Etsuo Fukuda, Masayoshi Tazawa, Kazuyuki Miura, Tomiko Takano, Yuichi Satoguchi, Yuichiro Ozaki
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Patent number: 5408858Abstract: A bending machine having an upper punch containing portion, or beam, and a lower die containing portion, or beam, is modified by incorporating a controlled expandable pressure device whereby the pressure applied to a work material is uniformly distributed throughout the surface of the material. In a first embodiment, the device is mounted in the upper and lower machine portions; in a second embodiment, the device is mounted only in the upper machine portion; in a third embodiment, the device is mounted only in the lower machine portion; and in a fourth embodiment, segmented devices are mounted in the upper machine portion and a single, elongated device is mounted in the lower machine portion.Type: GrantFiled: January 24, 1994Date of Patent: April 25, 1995Assignee: Amada Engineering & Service Co., Inc.Inventor: Etsuo Fukuda
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Patent number: 5365766Abstract: A die assembly for use with a tool for bending flat metal stock, and including a pair of elongated plate members in the lower die member each having a surface to support a piece of flat metal stock, the plate members being pivotably connected and maintained approximately 180 degrees apart when a bending force is not applied to the metal stock. A surface of an expandable pressure container is positioned in contact with a plate support member, the pressure within the container being controlled in a manner such that the vertical position of the plate support member is fixed such that the plate members assume a selected angular orientation to enable the tool to form the desired bend in the metal stock.Type: GrantFiled: May 18, 1993Date of Patent: November 22, 1994Assignee: Amada Engineering & Service Co., Inc.Inventors: Yukio Takahashi, Etsuo Fukuda