Patents by Inventor Etsuo Iijima
Etsuo Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130025789Abstract: A process including a main etching step under a first pressure using a gas containing at least HBr as an etching gas. The main etching is ended before a silicon oxide film is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr so as to completely expose the silicon oxide film. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.Type: ApplicationFiled: September 15, 2012Publication date: January 31, 2013Applicant: Tokyo Electron LimitedInventors: Etsuo IIJIMA, Norikazu Yamada
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Patent number: 8288286Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.Type: GrantFiled: December 16, 2008Date of Patent: October 16, 2012Assignee: Tokyo Electron LimitedInventors: Etsuo Iijima, Norikazu Yamada
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Patent number: 7531460Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.Type: GrantFiled: March 30, 2006Date of Patent: May 12, 2009Assignee: Tokyo Electron LimitedInventors: Etsuo Iijima, Meiki Koh
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Publication number: 20090098736Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.Type: ApplicationFiled: December 16, 2008Publication date: April 16, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Etsuo Iijima, Norikazu Yamada
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Patent number: 7504040Abstract: An RF power (Bottom RF) from a radio-frequency power source 12 is turned off (t5) and the supply of a He gas 14 to a back face of a wafer W is stopped (t5) when an end point detector 17 (EPD) detects an end point (t5), and a high-voltage DC power source 13 (HV) is turned off (t6) under the condition in which an RF power (Top RF) from a radio-frequency power source 11 is controlled to fall within a range in which etching does not progress and plasma discharge can be maintained (t5). This process enables the inhibition of the adhesion of particles while an etching amount is accurately controlled.Type: GrantFiled: February 28, 2007Date of Patent: March 17, 2009Assignee: Tokyo Electron LimitedInventors: Etsuo Iijima, Hiroshi Tsuchiya
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Patent number: 7476624Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.Type: GrantFiled: June 7, 2002Date of Patent: January 13, 2009Assignee: Tokyo Electron LimitedInventors: Etsuo Iijima, Norikazu Yamada
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Publication number: 20080261406Abstract: An etching method capable of increasing the selectivity of a polysilicon film to a silicon oxide film and suppressing recess formation on a silicon base layer. That part of the polysilicon film of a wafer transferred into a processing vessel which is exposed through an opening is etched so as to slightly remain on a gate oxide film. The pressure in a processing space is set to 66.7 Pa, HBr gas and He gas are supplied to the processing space, and a microwave of 2.45 GHz is supplied to a radial line slot antenna. The polysilicon film is etched by plasma generated from the HBr gas so as to be completely removed, the exposed gate oxide film is etched, and a resist film and an anti-reflection film are etched.Type: ApplicationFiled: September 26, 2007Publication date: October 23, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Etsuo IIJIMA, Katsumi Horiguchi
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Publication number: 20070184657Abstract: An etching method includes the step of forming recesses by performing a plasma etching on a target layer of a target object in a processing chamber of a plasma processing apparatus. The plasma etching is performed by using a mask, which is formed on the target layer and is provided with opening patterns including a dense patterned region and a sparse patterned region, such that portions of the target layer exposed through the opening pattern are etched by a plasma to form the recesses; and the plasma is exited by introducing a processing gas. A ratio of a flow rate of HBr to a flow rate of Cl2 (HBr/Cl2) is greater than or equal to about 1.2 and a ratio of a flow rate of the fluorine-containing gas to the flow rate of HBr (fluorine-containing gas/HBr) is greater than or equal to about 1.0.Type: ApplicationFiled: February 5, 2007Publication date: August 9, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Etsuo IIJIMA, Takamichi KIKUCHI
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Publication number: 20070148364Abstract: An RF power (Bottom RF) from a radio-frequency power source 12 is turned off (t5) and the supply of a He gas 14 to a back face of a wafer W is stopped (t5) when an end point detector 17 (EPD) detects an end point (t5), and a high-voltage DC power source 13 (HV) is turned off (t6) under the condition in which an RF power (Top RF) from a radio-frequency power source 11 is controlled to fall within a range in which etching does not progress and plasma discharge can be maintained (t5). This process enables the inhibition of the adhesion of particles while an etching amount is accurately controlled.Type: ApplicationFiled: February 28, 2007Publication date: June 28, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Etsuo Iijima, Hiroshi Tsuchiya
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Patent number: 7183217Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.Type: GrantFiled: June 7, 2002Date of Patent: February 27, 2007Assignee: Tokyo Electron LimitedInventors: Etsuo Iijima, Akiteru Koh
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Publication number: 20060172546Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.Type: ApplicationFiled: March 30, 2006Publication date: August 3, 2006Applicant: TOKYO ELECTON LIMITEDInventors: Etsuo Iijima, Meiki Koh
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Publication number: 20060081337Abstract: A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode serving as a cathode electrode, and a second electrode grounded to serve as an anode electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. The second electrode includes a conductive counter surface facing the first electrode and exposed to the plasma generation region.Type: ApplicationFiled: December 2, 2005Publication date: April 20, 2006Inventors: Shinji Himori, Kimihiro Higuchi, Tatsuo Matsudo, Etsuo Iijima, Hiroharu Ito, Shoichiro Matsuyama, Noriaki Imai, Kazuya Nagaseki
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Publication number: 20040192056Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.Type: ApplicationFiled: December 15, 2003Publication date: September 30, 2004Inventors: Etsuo Iijima, Norikazu Yamada
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Publication number: 20040171254Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.Type: ApplicationFiled: December 22, 2003Publication date: September 2, 2004Inventors: Etsuo Iijima, Meiki Koh
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Publication number: 20040076762Abstract: An RF power (Bottom RF) from a radio-frequency power source 12 is turned off (t5) and the supply of a He gas 14 to a back face of a wafer W is stopped (t5) when an end point detector 17 (EPD) detects an end point (t5), and a high-voltage DC power source 13 (HV) is turned off (t6) under the condition in which an RF power (Top RF) from a radio-frequency power source 11 is controlled to fall within a range in which etching does not progress and plasma discharge can be maintained (t5). This process enables the inhibition of the adhesion of particles while an etching amount is accurately controlled.Type: ApplicationFiled: September 5, 2003Publication date: April 22, 2004Inventor: Etsuo Iijima
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Publication number: 20040009667Abstract: When simultaneously etching areas such as an n-type area and a p-type area doped with different dopants or having different dope quantities, the inconsistency in the shapes of elements formed at the individual areas is minimized and the occurrence of a gate oxide film breakdown is prevented by first executing a main etching step (first etching step) during which, a polysilicon film layer 204 is etched until a gate oxide film 202 becomes partially exposed by setting the pressure inside a processing chamber to 20 mTorr or lower, setting the high-frequency power applied to a lower electronic to 0.15 W/cm2 or higher, supplying a processing gas containing at least HBr gas into the processing chamber and using mask patterns as masks and then executing an over-etching step (a second etching step) during which N2 gas is added into the processing gas and any remaining portions of the polysilicon film layer left unetched during the main etching step are removed through etching.Type: ApplicationFiled: February 6, 2003Publication date: January 15, 2004Inventors: Etsuo Iijima, Akiteru Koh