Patents by Inventor Etsuo Yamada
Etsuo Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8280665Abstract: A calibration device for an on-vehicle camera includes an image receiving portion receiving an image of an area around a vehicle taken by an on-vehicle camera, a viewpoint transformation portion performing a viewpoint transformation on the image to obtain a transformed image, a region setting portion setting a recognition target region on the transformed image according to coordinates of the calibration index set in accordance with vehicle models, where the recognition target region includes therein the calibration index, a calibration point detecting portion detecting a calibration point positioned within the calibration index included in the recognition target region, and a calibration calculating portion calibrating the on-vehicle camera in accordance with coordinates of the calibration point in a reference coordinate system and in accordance with coordinates of the calibration point in a camera coordinate system.Type: GrantFiled: September 2, 2009Date of Patent: October 2, 2012Assignee: Aisin Seiki Kabushiki KaishaInventors: Yoshihiro Nakamura, Etsuo Yamada
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Patent number: 8077199Abstract: A target position identifying apparatus includes a color difference converting section for processing pixel values of an image of a target comprised of combination of a first color and a second color obtained from the target under influence of ambient light, thus generating a color component value of the first color, a color component value of the second color and a luminance value, a color region determining section for determining region of the first color and region of the second color, based on the first color component value and the second color component value, with using a determination condition based on either luminance of the captured image or the luminance value, a border detecting section for detecting border between the first color and the second color in the target based on result of the determination by the color region determining section and a target position calculating section for calculating the position of the target on the image based on result of the border detection by the border detecType: GrantFiled: July 17, 2009Date of Patent: December 13, 2011Assignee: Aisin Seiki Kabushiki KaishaInventors: Yoshihiro Nakamura, Etsuo Yamada, Keiji Takagi, Masataka Chiba
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Publication number: 20110102581Abstract: A target position identifying apparatus includes a color difference converting section for processing pixel values of an image of a target comprised of combination of a first color and a second color obtained from the target under influence of ambient light, thus generating a color component value of the first color, a color component value of the second color and a luminance value, a color region determining section for determining region of the first color and region of the second color, based on the first color component value and the second color component value, with using a determination condition based on either luminance of the captured image or the luminance value, a border detecting section for detecting border between the first color and the second color in the target based on result of the determination by the color region determining section and a target position calculating section for calculating the position of the target on the image based on result of the border detection by the border detecType: ApplicationFiled: July 17, 2009Publication date: May 5, 2011Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Yoshihiro Nakamura, Etsuo Yamada, Keiji Takagi, Masataka Chiba
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Publication number: 20100082281Abstract: A calibration device for an on-vehicle camera includes an image receiving portion receiving an image of an area around a vehicle taken by an on-vehicle camera, a viewpoint transformation portion performing a viewpoint transformation on the image to obtain a transformed image, a region setting portion setting a recognition target region on the transformed image according to coordinates of the calibration index set in accordance with vehicle models, where the recognition target region includes therein the calibration index, a calibration point detecting portion detecting a calibration point positioned within the calibration index included in the recognition target region, and a calibration calculating portion calibrating the on-vehicle camera in accordance with coordinates of the calibration point in a reference coordinate system and in accordance with coordinates of the calibration point in a camera coordinate system.Type: ApplicationFiled: September 2, 2009Publication date: April 1, 2010Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Yoshihiro Nakamura, Etsuo Yamada
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Patent number: 7402502Abstract: A method of manufacturing a semiconductor device includes providing a matrix frame which includes a plurality of die pads, mounting a semiconductor chip on the respective die pads, and sealing the semiconductor chip in blocks. After the semiconductor chip is sealed by the sealing resin, inner leads which are extended from the sealing resin are punched by a punching blade. Then, the block is diced to individual semiconductor devices by a rotary blade.Type: GrantFiled: September 17, 2004Date of Patent: July 22, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Etsuo Yamada
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Patent number: 7110498Abstract: An image reading apparatus includes a DC/DC power supply which supplies power to at least part of the apparatus, a photodetector array including two-dimensionally arranged photoelectric conversion elements, and a line selector and reading circuit which read signals from the photoelectric conversion elements for each row in the photodetector array as a unit. A line driving signal in the line selector is set to be synchronized with a reference clock for defining the oscillation frequency of the DC/DC power supply and have a period of an integer multiple of the reference clock. A sample/hold signal for determining the timing at which a signal read from the photodetector array is sampled/held is output at a predetermined phase timing of each period of the line driving signal.Type: GrantFiled: September 10, 2004Date of Patent: September 19, 2006Assignee: Canon Kabushiki KaishaInventor: Etsuo Yamada
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Patent number: 6913951Abstract: A semiconductor device which is sealed with a plastic sealing layer and whose thickness is regulated to be below a given value is known. Since the thickness of the device is small, and the thickness of the upper portion of the plastic sealing layer and the thickness of the lower portion thereof are different from each other, the plastic sealing layer becomes warped, thus causing a crack on the side of the semiconductor chip. To solve this problem, the semiconductor device according to the present invention comprises a semiconductor chip on which a plurality of grooves are defined. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.Type: GrantFiled: January 14, 2003Date of Patent: July 5, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Etsuo Yamada, Kenji Nagasaki, Yasushi Shiraishi, Kazuhiko Sera
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Publication number: 20050142814Abstract: A method of manufacturing a semiconductor device includes providing a matrix frame which includes a plurality of die pads, mounting a semiconductor chip on the respective die pads, and sealing the semiconductor chip in blocks. After the semiconductor chip is sealed by the sealing resin, inner leads which are extended from the sealing resin are punched by a punching blade. Then, the block is diced to individual semiconductor devices by a rotary blade.Type: ApplicationFiled: September 17, 2004Publication date: June 30, 2005Inventor: Etsuo Yamada
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Publication number: 20050058252Abstract: An image reading apparatus includes a DC/DC power supply which supplies power to at least part of the apparatus, a photodetector array including two-dimensionally arranged photoelectric conversion elements, and a line selector and reading circuit which read signals from the photoelectric conversion elements for each row in the photodetector array as a unit. A line driving signal in the line selector is set to be synchronized with a reference clock for defining the oscillation frequency of the DC/DC power supply and have a period of an integer multiple of the reference clock. A sample/hold signal for determining the timing at which a signal read from the photodetector array is sampled/held is output at a predetermined phase timing of each period of the line driving signal.Type: ApplicationFiled: September 10, 2004Publication date: March 17, 2005Inventor: Etsuo Yamada
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Publication number: 20030102545Abstract: A semiconductor device which is sealed with a plastic sealing layer and whose thickness is regulated to be below a given value is known. Since the thickness of the device is small, and the thickness of the upper portion of the plastic sealing layer and the thickness of the lower portion thereof are different from each other, the plastic sealing layer becomes warped, thus causing a crack on the side of the semiconductor chip.Type: ApplicationFiled: January 14, 2003Publication date: June 5, 2003Inventors: Etsuo Yamada, Kenji Nagasaki, Yasushi Shiraishi, Kazuhiko Sera
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Patent number: 6534845Abstract: A semiconductor. device comprises a semiconductor chip on which a plurality of grooves are defined, thus acting as a resisting member, the effect of which is to prevent the semiconductor chip from bending. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.Type: GrantFiled: June 9, 1999Date of Patent: March 18, 2003Assignee: Oki Electric Industry Co., Ltd.Inventors: Etsuo Yamada, Kenji Nagasaki, Yasushi Shiraishi, Kazuhiko Sera
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Patent number: 6403398Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.Type: GrantFiled: December 12, 2000Date of Patent: June 11, 2002Assignee: Oki Electric Industry Co, Ltd.Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada
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Patent number: 6262482Abstract: In a semiconductor device 1 according to the present invention, a plurality of inner leads are bonded to a front surface of a semiconductor element 11 covered by a package 10, with bent portions 17 formed at some inner leads 13a among the plurality of inner leads 13 and the front ends of the bent portions 17 exposed at a front surface of the package 10. This structure ensures that the semiconductor element is not caused to move vertically inside the forming die by the pressure of the liquid resin or the like during the sealing process.Type: GrantFiled: October 7, 1998Date of Patent: July 17, 2001Assignee: Oki Electric Industry Co., Ltd.Inventors: Yasushi Shiraishi, Kazuhiko Sera, Etsuo Yamada, Kenji Nagasaki
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Patent number: 6258621Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.Type: GrantFiled: February 1, 1999Date of Patent: July 10, 2001Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Hiroshi Kawano, Etsuo Yamada, Yasushi Shiraishi
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Publication number: 20010001217Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.Type: ApplicationFiled: December 12, 2000Publication date: May 17, 2001Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada
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Patent number: 6208021Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.Type: GrantFiled: February 26, 1997Date of Patent: March 27, 2001Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada
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Patent number: 6097083Abstract: A resin mold type semiconductor device, which is crack resistant and can be made relatively thin, includes a semiconductor chip, a lead member arranged in a manner such that an one side face of a head portion thereof touches a surface of the semiconductor chip, a wire for electrically connecting the surface of the semiconductor chip and another side face of the lead member, an adhesive member for adhering the one side face of the lead member and a peripheral face of the semiconductor chip, and a package for molding the semiconductor chip, a part of the lead, the wire and the adhesive member by synthetic resin. Further, the lead member may be provided with a concave portion in the one side face and possibly also a groove extending from the concave portion to an end of the lead.Type: GrantFiled: April 10, 1997Date of Patent: August 1, 2000Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Etsuo Yamada, Yasushi Shiraishi
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Patent number: 6002181Abstract: A resin molded type semiconductor device has an inner portion sandwiched between two outer surfaces. The device includes a chip support with a first, inwardly facing surface and a second, outwardly facing surface. The device also includes a semiconductor element with a first, inwardly facing surface and a second, outwardly facing surface. The respective first surfaces of the chip support and semiconductor element are fixed to each other. A mold resin is provided to seal the entire semiconductor device except for the respective second surfaces of the chip support and semiconductor element which remain exposed as part of the two outer surfaces of the device, in order to keep the semiconductor device thin.Type: GrantFiled: October 23, 1995Date of Patent: December 14, 1999Assignee: Oki Electric Industry Co., Ltd.Inventors: Etsuo Yamada, Yasushi Shiraishi, Hiroshi Kawano, Shinji Ohuchi, Hidekazu Nasu
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Patent number: 5969410Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.Type: GrantFiled: April 29, 1997Date of Patent: October 19, 1999Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Hiroshi Kawano, Etsuo Yamada, Yasushi Shiraishi
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Patent number: 5874783Abstract: A semiconductor device includes connector leads which have an offset portion supported by the primary surface of a semiconductor chip on which electronics circuitry is formed into an integrated circuit. The offset portion is disposed near the contact pads for connecting the electronics circuitry. The remaining portion of the connector leads far from the contact pads is spaced from the primary surface by an adhesive strip of electrically insulative material. Bonding wires connect the connector leads to the contact pads. The total thickness of the package is reduced to accomplish a thinner and flatter semiconductor device.Type: GrantFiled: July 25, 1997Date of Patent: February 23, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Etsuo Yamada