Patents by Inventor Etsuro Morita
Etsuro Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8283252Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: September 14, 2009Date of Patent: October 9, 2012Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Patent number: 7867877Abstract: A method for manufacturing SOI wafers is provided which allows the obtaining of a thin SOI layer having uniform in-plane thickness. In this manufacturing method, an oxygen ion implanted layer is first formed on an active layer wafer. This is then laminated to a base wafer with a embedded oxide film interposed therebetween. The active layer wafer side of the laminated wafer is then ground to remove a portion thereof. The remaining surface side of the active layer wafer is removed by polishing or KOH etching to expose the oxygen ion implanted layer. Oxygen ions are implanted to a uniform depth within the plane of the oxygen ion implanted layer in this oxygen ion implanted layer. Subsequently, oxidizing treatment is carried out to form an oxide film on the exposed surface of the oxygen ion implanted layer. Moreover, this oxide film is removed together with the oxygen ion implanted layer by an HF solution. The remaining portion of the active layer wafer serves as a thin SOI layer.Type: GrantFiled: January 28, 2005Date of Patent: January 11, 2011Assignee: Sumco CorporationInventors: Etsuro Morita, Akihiko Endo
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Publication number: 20100009605Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: ApplicationFiled: September 14, 2009Publication date: January 14, 2010Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Patent number: 7589023Abstract: A method of manufacturing a semiconductor wafer, comprising the step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by using an abrasive cloth with a semiconductor wafer sink rate different in polishing from that of the other abrasive cloth for one of a polishing cloth (14) on an upper surface plate (12) and a polishing cloth (15) on a lower surface plate (13) so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer (W), or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: April 23, 2001Date of Patent: September 15, 2009Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Publication number: 20070161199Abstract: A method for manufacturing SOI wafers is provided which allows the obtaining of a thin SOI layer having uniform in-plane thickness. In this manufacturing method, an oxygen ion implanted layer is first formed on an active layer wafer. This is then laminated to a base wafer with a embedded oxide film interposed therebetween. The active layer wafer side of the laminated wafer is then ground to remove a portion thereof. The remaining surface side of the active layer wafer is removed by polishing or KOH etching to expose the oxygen ion implanted layer. Oxygen ions are implanted to a uniform depth within the plane of the oxygen ion implanted layer in this oxygen ion implanted layer. Subsequently, oxidizing treatment is carried out to form an oxide film on the exposed surface of the oxygen ion implanted layer. Moreover, this oxide film is removed together with the oxygen ion implanted layer by an HF solution. The remaining portion of the active layer wafer serves as a thin SOI layer.Type: ApplicationFiled: January 28, 2005Publication date: July 12, 2007Inventor: Etsuro Morita
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Publication number: 20040025983Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute. ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is an axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting point of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperatures in a range of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, tree of COP's, and substantially free of contamination such as Fe and of occurrence of slip, is obtained.Type: ApplicationFiled: July 28, 2003Publication date: February 12, 2004Inventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata
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Patent number: 6663708Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is and axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.Type: GrantFiled: September 22, 2000Date of Patent: December 16, 2003Assignee: Mitsubishi Materials Silicon CorporationInventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata
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Publication number: 20030104698Abstract: An object of the present invention is to provide a semiconductor wafer having a front and a back surfaces polished so as to have different glossiness from each other, yet with a lower cost. The glossiness of the front surface and the back surface can be selected arbitrarily. In a double-sided polisher with no sun gear, silicon wafers W are inserted in respective holding holes 11a of a carrier plate 11. The wafers W are placed with their back surfaces facing up. An expanded urethane foam pad 14 is pressed against the back surfaces of the wafers W and a non-woven fabric pad 15 is pressed against the front surfaces of the wafers W. A carrier holder 20 and thus the carrier plate 11 are then driven to make a circular motion associated with no rotation on their own axes within a horizontal plane while supplying a slurry to the wafers W from an upper surface plate 12 side.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida