Patents by Inventor Etsushi Adachi

Etsushi Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6565401
    Abstract: A getter film is formed on an inner surface of a funnel portion of a cathode ray tube, and an inner conductor of the cathode ray tube is heated by a heating unit. According to this heating, the gas which is physically adsorbed by the inner conductor of the cathode ray tube other than the getter film is discharged and then chemically adsorbed again by the getter film, whereby a degree of vacuum in the cathode ray tube can be increased.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: May 20, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeshi Sugano, Etsushi Adachi, Chikayuki Nakamura, Wataru Imanishi
  • Patent number: 5889330
    Abstract: In a semiconductor device and a method of fabrication thereof, a resin film forms an interlayer film of the semiconductor device having a multilayer interconnection structure, and is formed by only one coating using coating liquid containing silicone ladder polymers represented by the chemical formula: (HO).sub.2 (R.sub.2 Si.sub.2 O.sub.3).sub.n H.sub.2. As a result, it is possible to improve long-term reliability of electric characteristics or the like, and simplify a process.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: March 30, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Nishimura, Hiroshi Adachi, Etsushi Adachi, Shigeyuki Yamamoto, Shintaro Minami, Shigeru Harada, Toru Tajima, Kimio Hagi
  • Patent number: 5728630
    Abstract: In a semiconductor device and a method of fabrication thereof, a resin film forms an interlayer film of the semiconductor device having a multilayer interconnection structure, and is formed by only one coating using coating liquid containing silicone ladder polymers represented by the chemical formula: (HO).sub.2 (R.sub.2 Si.sub.2 O.sub.3).sub.n H.sub.2. As a result, it is possible to improve long-term reliability of electric characteristics or the like, and simplify a process.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: March 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Nishimura, Hiroshi Adachi, Etsushi Adachi, Shigeyuki Yamamoto, Shintaro Minami, Shigeru Harada, Toru Tajima, Kimio Hagi
  • Patent number: 5604380
    Abstract: In a semiconductor device and a method of fabrication thereof, a resin film forms an interlayer film of the semiconductor device having a multilayer interconnection structure, and is formed by only one coating using coating liquid containing silicone ladder polymers represented by the chemical formula: (HO).sub.2 (R.sub.2 Si.sub.2 O.sub.3).sub.n H.sub.2. As a result, it is possible to improve long-term reliability of electric characteristics or the like, and simplify a process.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: February 18, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Nishimura, Hiroshi Adachi, Etsushi Adachi, Shigeyuki Yamamoto, Shintaro Minami, Shigeru Harada, Toru Tajima, Kimio Hagi
  • Patent number: 5600151
    Abstract: A semiconductor device having a stress-buffering film which is effective in buffering the stress caused by a molding resin during sealing, the stress-buffering film being made of a silicone ladder resin represented by formula (I) ##STR1## wherein each end group R may be the same or different and represents a hydrogen atom or an alkyl group, each side chain R' may be the same or different and represents a cyclohexyl group, a lower alkyl group, or a photopolymerizable unsaturated group, and n is an integer of 10 or larger.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: February 4, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hisoshi Adachi, Shigeyuki Yamamoto, Hiroyuki Nishimura, Shintaro Minami, Tooru Tazima, Hiroshi Tobimatsu
  • Patent number: 5510653
    Abstract: Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: April 23, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noriaki Fujiki, Shigeru Harada, Hiroshi Adachi, Etsushi Adachi
  • Patent number: 5306947
    Abstract: The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: April 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Adachi, Hirozoh Kanegae, Hiroshi Mochizuki, Masanori Obata, Takemi Endoh, Kimio Hagi, Shigeru Harada, Kazuhito Matsukawa, Akira Ohhisa, Etsushi Adachi
  • Patent number: 5278451
    Abstract: A semiconductor device sealed with mold resin is disclosed. The device includes a semiconductor substrate having a main surface and an element formed on the main surface of the semiconductor substrate. A stress buffering film for protecting at least the element from stress of the mold resin is provided on the semiconductor substrate so as to cover at least the element. The entire semiconductor device is covered and sealed with mold resin. The stress buffering film is formed of organo-silicone ladder polymer having a hydroxyl group at its end. In the semiconductor device, water does not get into an interface of the stress buffering film and the underlying substrate, resulting in an enhancement of the moisture resistance of the semiconductor device.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: January 11, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Hiroshi Mochizuki
  • Patent number: 5183846
    Abstract: Disclosed herein is a silicone ladder polymer coating composition containing silicone ladder polymer which is expressed in the following general formula: ##STR1## where R.sub.1 represents the same or different types of phenyl groups or lower alkyl groups, R.sub.2 represents the same or different types of hydrogen atoms or lower alkyl groups, and n represents an integer of 20 to 1000, an aromatic organic solvent which is so added that solid matter occupies 5 to 30 percent by weight, and a silane coupling agent of 150 to 3000 p.p.m. with respect to the polymer.
    Type: Grant
    Filed: July 2, 1991
    Date of Patent: February 2, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiko Aiba, Hiroshi Adachi, Etsushi Adachi
  • Patent number: 5180691
    Abstract: The disclosed is a method of manufacturing a semiconductor device sealed with molding resin. An aluminum interconnection including an aluminum electrode pad is formed on a semiconductor substrate having an element. A silicone ladder polymer expressed by the following general formula is formed on the semiconductor substrate to cover the element. The silicone ladder polymer film is selectively etched by an aromatic organic solvent to expose the surface of the aluminum electrode pad. The temperature of the silicone ladder polymer film is elevated at a temperature elevating rate of 20.degree. C./min or more, and then, the silicone ladder polymer film is cooled at a cooling rate of 20.degree. C./min or more to form a cured stress buffering protective film for buffering a stress applied to the element. ##STR1## (in the formula, n is an integer which makes the weight-average molecular weight be in the range of 100,000 to 200,000.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: January 19, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Hiroshi Mochizuki, Hirozoh Kanegae
  • Patent number: 5087553
    Abstract: A method for transferring patterns on a silicone ladder type resin, which comprises: applying onto a substrate a silicone ladder type resin to be represented by the following general formula (I) ##STR1## (where: R.sub.1 denotes a phenyl group or a lower alkyl group, and two R.sub.1 's may be the same or different kinds; R.sub.2 denotes hydrogen atom or a lower alkyl group, and four R.sub.2 's may be the same or different kinds; and n represents an integer of from 5 to 1,000); drying the thus applied resin layer; thereafter applying onto the resin layer a cresol novolac type positive photo-resist; forming a predetermined pattern in the photo-resist layer; subjecting the photo-resist layer to pretreatment; and finally etching the silicone ladder type resin.An etching liquid for etching a silicone ladder type resin, which comprises an aromatic type solvent.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: February 11, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Adachi, Etsushi Adachi, Yoshiko Aiba, Osamu Hayashi
  • Patent number: 5081202
    Abstract: High purity phenyl silicone ladder polymer, and a method for producing such polymer, suitable for use as the protective film, the interlayer insulating film, etc. in the fabrication of semiconductor elements, which polymer contains therein 1 ppm or below of each of sodium, potassium, iron, copper, lead and chlorine, and 1 ppb or below of each of uranium and thorium, and which is represented by the following general formula (I): ##STR1## (where: R.sub.1 to R.sub.4 denote respectively hydrogen or a lower alkyl group; n is an integer of from 8 to 1,000); or the following general formula (II): ##STR2## (where: n is an integer of from 8 to 1,600).
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: January 14, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Adachi, Etsushi Adachi, Osamu Hayashi, Kazuo Okahashi
  • Patent number: 5057336
    Abstract: A material for forming a high purity thin film which includes a silicone ladder polymer dissolved in an organic solvent is applied to a substrate to form a thin film thereon. The thin film is then heated, thereby removing the solvent and simultaneously curing the thin film. Subsequently, the cured thin film is exposed to an oxygen plasma to form a high purity SiO.sub.2 thin film on the substrate. Although the method consists of simple processes and employs low treatment temperatures, it is capable of forming a high purity SiO.sub.2 thin film which exhibits excellent step coverage and high dielectric breakdown strength.
    Type: Grant
    Filed: June 5, 1990
    Date of Patent: October 15, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Osamu Hayashi, Kazuo Okahashi
  • Patent number: 5023204
    Abstract: A stress relaxation protective layer made of a silicone material is formed on a coating covering a circuit disposed on a substrate of a semiconductor device, and a predetermined depth of the surface of the stress relaxation protective layer is modified. A resist is formed on the thus-modified surface of the stress relaxation protective layer, and the thus-formed resist is patterned so that the resist in a predetermined region is removed. The stress relaxation protective layer in the region from which the above-described resist has been removed is removed by etching, and the remaining resist is removed. Next, the coating layer in the region from which the stress relaxation protective layer has been removed is removed by etching with the remaining stress relaxation protective layer used as a mask so that the circuit is exposed.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: June 11, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Osamu Hayashi, Kazuo Okahashi