Patents by Inventor Etsuya Morita

Etsuya Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7523429
    Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: April 21, 2009
    Assignee: Takumi Technology Corporation
    Inventors: Armen Kroyan, Youping Zhang, Etsuya Morita, Adrianus Ligtenberg
  • Patent number: 6974653
    Abstract: Methods for using critical dimension test marks (test marks) for the rapid determination of the best focus position of lithographic processing equipment and critical dimension measurement analysis across a wafer's surface are described. In a first embodiment, a plurality of test mark arrays are distributed across the surface of a wafer, a different plurality being created at a plurality of focus positions. Measurement of the length or area of the resultant test marks allows for the determination of the best focus position of the processing equipment. Critical dimension measurements at multiple points on a wafer with test marks allow for the determination of process accuracy and repeatability and further allows for the real-time detection of process degradation. Using test marks which require only a relatively simple optical scanner and sensor to measure their length or area, it is possible to measure hundreds of measurement values across a wafer in thirty minutes.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: December 13, 2005
    Assignee: Nikon Precision Inc.
    Inventors: Frank C. Leung, Etsuya Morita, Christopher Howard Putnam, Holly H. Magoon, Ronald A. Pierce, Norman E. Roberts
  • Publication number: 20050188338
    Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
    Type: Application
    Filed: February 18, 2005
    Publication date: August 25, 2005
    Inventors: Armen Kroyan, Youping Zhang, Etsuya Morita, Adrianus Ligtenberg
  • Publication number: 20030211700
    Abstract: Methods for using critical dimension test marks (test marks) for the rapid determination of the best focus position of lithographic processing equipment and critical dimension measurement analysis across a wafer's surface are described. In a first embodiment, a plurality of test mark arrays are distributed across the surface of a wafer, a different plurality being created at a plurality of focus positions. Measurement of the length or area of the resultant test marks allows for the determination of the best focus position of the processing equipment. Critical dimension measurements at multiple points on a wafer with test marks allow for the determination of process accuracy and repeatability and further allows for the real-time detection of process degradation. Using test marks which require only a relatively simple optical scanner and sensor to measure their length or area, it is possible to measure hundreds of measurement values across a wafer in thirty minutes.
    Type: Application
    Filed: December 4, 2002
    Publication date: November 13, 2003
    Applicant: Nikon Precision Inc.
    Inventors: Frank C. Leung, Etsuya Morita, Christopher Howard Putnam, Holly H. Magoon, Ronald A. Pierce, Norman E. Roberts
  • Patent number: 5835227
    Abstract: A method and apparatus for determining performance characteristics in lithographic tools includes projecting a predetermined image with a projection system having a known predetermined performance characteristic to obtain data indicative of the relationship between the size of the projected image and the predetermined performance characteristic. The same image is then projected in a system having an unknown value for the predetermined performance characteristic. The predetermined performance characteristic for the system under consideration is then determined based on the data obtained when the image was projected in the system having the known predetermined performance characteristic.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: November 10, 1998
    Assignee: Nikon Precision Inc.
    Inventors: Ilya Grodnensky, Etsuya Morita, Kyoichi Suwa, Shigeru Hirukawa