Patents by Inventor Etsuyoshi Kobori

Etsuyoshi Kobori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060145268
    Abstract: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.
    Type: Application
    Filed: March 6, 2006
    Publication date: July 6, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Etsuyoshi Kobori
  • Patent number: 7034367
    Abstract: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: April 25, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Etsuyoshi Kobori
  • Patent number: 7022619
    Abstract: After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: April 4, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michinari Yamanaka, Hiroshi Yuasa, Tetsuo Satake, Etsuyoshi Kobori, Takeshi Yamashita, Susumu Matsumoto
  • Publication number: 20040169252
    Abstract: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.
    Type: Application
    Filed: February 20, 2004
    Publication date: September 2, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Etsuyoshi Kobori
  • Patent number: 6713847
    Abstract: Wiring of the Dual-Damascene structure is formed without using the CMP method. As shown in FIG. 1A, oxygen ions are implanted from an upper surface under the condition that the oxygen ions reach a position a little deeper than the thickness t1 of the copper film 11 on the SiO2 layer 2. Due to the foregoing, as shown in FIG. 1B, the copper film 11 on the SiO2 layer 2 and the copper films on the upper portions of the first wiring section 18 and the second wiring section 19 are oxidized, and the oxidized layer 13 is formed. Since the dielectric constant of copper oxide is high, the first wiring section 18 and the second wiring section 19 are insulated from each other. Therefore, it is possible to obtain a highly reliable wiring structure easily.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: March 30, 2004
    Assignee: Rohm Co., Ltd.
    Inventor: Etsuyoshi Kobori
  • Publication number: 20030186537
    Abstract: After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 2, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Michinari Yamanaka, Hiroshi Yuasa, Tetsuo Satake, Etsuyoshi Kobori, Takeshi Yamashita, Susumu Matsumoto
  • Patent number: 6100190
    Abstract: Wiring of the Dual-Damascene structure is formed without using the CMP method.As shown in FIG. 1A, oxygen ions are implanted from an upper surface under the condition that the oxygen ions reach a position a little deeper than the thickness t1 of the copper film 11 on the SiO.sub.2 layer 2. Due to the foregoing, as shown in FIG. 1B, the copper film 11 on the SiO.sub.2 layer 2 and the copper films on the upper portions of the first wiring section 18 and the second wiring section 19 are oxidized, and the oxidized layer 13 is formed. Since the dielectric constant of copper oxide is high, the first wiring section 18 and the second wiring section 19 are insulated from each other. Therefore, it is possible to obtain a highly reliable wiring structure easily.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: August 8, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Etsuyoshi Kobori