Abstract: A digitally compensated analog-to-digital converter (ADC) provides improved linearity by generating calibration values having higher resolution than the output signal generated during a normal conversion. During a calibration value generation operation, the converter performs a normal conversion, then performs an additional conversion, thereby generating a high resolution calibration value which is then rounded and stored in a memory device. The converter includes a flash ADC which converts an analog input signal received through a multiplexer and sample-hold amplifier to a digital signal. The flash ADC provides control signals to a multibit digital-to-analog converter which generates the analog reconfiguration signal during multi-stage conversions. A digital correction circuit receives the digital signals from several multi-stage conversion and generates a corrected signal.