Abstract: Microelectronics having form factors (e.g., dimensions and functionality) comparable with traditional microelectronics, but with considerably simplified design, and their methods of manufacture are provided. Microelectronics and methods that implement microelectronics are capable of being forming without the need for through-vias. Exemplary dielectrics in these embodiments include, but are not limited to, high Q, temperature stable and high k dielectrics. Microelectronics and methods are capable of combination with any other passive electronic component such as a resistor or inductor further improving functionality and reducing space requirements on the circuit. Microelectronics and methods are configured to be mounted to a short block or other device without the use of a through-via, simplifying connection to a circuit.

Abstract: Capacitors having form factors (e.g., dimensions and functionality) comparable with traditional single layer capacitors, but with considerably higher capacitance and methods of their manufacture are provided. Capacitors and methods that implement capacitors where at least one of the dielectric layers is reduced in thickness post firing to produce a device robust enough for automated handling and provide a stable surface for wire-bonding are also provided. Capacitors and methods that implement an internal electrode between at least two layers of pre-fired ceramic dielectric are also provided. Capacitors and methods that implement the integration of multiple dielectric types in a single device producing high frequency performance characteristics are also provided. Capacitors and dielectrics that implement the combination of a multi-layer capacitor with a thin single layer capacitor to further increase operating frequency and capacitance are also provided.

Abstract: Capacitors having form factors (e.g., dimensions and functionality) comparable with traditional single layer capacitors, but with considerably higher capacitance and methods of their manufacture are provided. Capacitors and methods that implement capacitors where at least one of the dielectric layers is reduced in thickness post firing to produce a device robust enough for automated handling and provide a stable surface for wire-bonding are also provided. Capacitors and methods that implement an internal electrode between at least two layers of pre-fired ceramic dielectric are also provided. Capacitors and methods that implement the integration of multiple dielectric types in a single device producing high frequency performance characteristics are also provided. Capacitors and dielectrics that implement the combination of a multi-layer capacitor with a thin single layer capacitor to further increase operating frequency and capacitance are also provided.

Abstract: A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.

Abstract: A multi-layer ceramic capacitor (MLCC) device includes a ceramic chip having electrically conductive layers embedded within the chip that form one or more capacitors connected by one or more vias to one or more upwardly facing wire-bondable pads on the top side of the device. One embodiment includes electrically conductive layers that form at least two stacked capacitors connected by vias to multiple upwardly facing wire-bondable pads on the top side, whereby the MLCC device has a reduced footprint while avoiding solder fillets. The wire-bondable pads may lie m a common plane or be pyramidally stepped. Metallization on the PCB-facing bottom side and at least one of the ends of the ceramic chip of another embodiment forms a downwardly facing capacitor terminal.

Abstract: A high capacitance single layer ceramic capacitor structure having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and bottom surfaces and a metallization pad electrically isolated from the metallization side and bottom surfaces positioned on a top surface of the ceramic body.

Abstract: A multi-layer ceramic capacitor (MLCC) device includes a ceramic chip having electrically conductive layers embedded within the chip that form one or more capacitors connected by one or more vias to one or more upwardly facing wire-bondable pads on the top side of the device. One embodiment includes electrically conductive layers that form at least two stacked capacitors connected by vias to multiple upwardly facing wire-bondable pads on the top side, whereby the MLCC device has a reduced footprint while avoiding solder fillets. The wire-bondable pads may lie in a common plane or be pyramidally stepped. Metallization on the PCB-facing bottom side and at least one of the ends of the ceramic chip of another embodiment forms a downwardly facing capacitor terminal.

Abstract: A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.

Abstract: A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.

Abstract: A multi-layer ceramic capacitor (MLCC) device includes a ceramic chip having electrically conductive layers embedded within the chip that form one or more capacitors connected by one or more vias to one or more upwardly facing wire-bondable pads on the top side of the device. One embodiment includes electrically conductive layers that form at least two stacked capacitors connected by vias to multiple upwardly facing wire-bondable pads on the top side, whereby the MLCC device has a reduced footprint while avoiding solder fillets. The wire-bondable pads may lie in a common plane or be pyramidally stepped. Metallization on the PCB-facing bottom side and at least one of the ends of the ceramic chip of another embodiment forms a downwardly facing capacitor terminal.

Abstract: A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.

Abstract: A high capacitance single layer ceramic capacitor structure having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and bottom surfaces and a metallization pad electrically isolated from the metallization side and bottom surfaces positioned on a top surface of the ceramic body.