Abstract: An accumulative repeat encoder facilitates encoding data written to memory, such that parity data is generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data is stored in memory. During a read operation, a decoder component utilizes the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component is iterative and provides one or more decoding results based on probabilities that symbols or bits comprising the data have correct values. The decoder component analyzes a decoding result and references a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result is determined to represent the original data and is provided as an output.

Abstract: Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Abstract: Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

Abstract: An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.

Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

Abstract: System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

Abstract: A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.

Abstract: The present invention pertains to a system that facilitates a determination of the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

Abstract: A system and method are disclosed for improved memory performance in a mobile device. A mobile device incorporating teachings disclosed herein may include, for example, a central processing unit (CPU) residing on a first chip. The mobile device may also include a memory system residing on a second chip. The memory system may include, for example, a memory controller and at least one type of memory combined in a single multi-chip package. The multi-chip package may effectively internalize higher pin count interfaces interconnecting the memory controller and the at least one type of memory. With some implementations, a high frequency, low pin-count external bus may form at least a portion of a link communicatively coupling the multi-chip package and the CPU. In practice, the high frequency, low pin-count external bus may physically connect to a bus interface residing on the first chip. The bus interface may be communicatively coupled to the CPU via an internal CPU bus also located on the first chip.

Abstract: The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

Abstract: The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

Abstract: The present invention provides for an apparatus and a method for testing and evaluating a transmission line. A set of command and data signals is received through an input/output interface. The command and data signals from the input/output interface are processed for controlling at least one relay. At least one switch is activated for testing a transmission signal line using the relay. The transmission signal line is tested based upon the activated switch.

Abstract: A demodulation circuit for demodulating a frequency diverse complex modulated carrier comprises an A/D converter generating a series of samples representing the modulated carrier, a mixer operating to mix the series of samples with a sine wave of one fourth the sampling frequency represented by a series of sine wave values occurring at the sampling frequency, and a decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples.

Abstract: A method for selecting a decimation phase of a decimation filter includes determining a phase strength value for each phase of a plurality of phases. The quantity of phases corresponds to the decimation factor of the decimation filter. The phase strength value for a particular phase group may be representative of the sum of the magnitudes of a plurality of phase values in such particular phase group. The phase strength value for a particular phase group may represent the sum of the squares of a plurality of phase values in the group. The phase of the decimation filter is set to retain the phase with the greatest phase strength value and to filter, or decimate, the other phases.

Abstract: A network node configured for transmitting and receiving data to and from other network nodes is able to adapt the transmission rate based on the network conditions. The node initially transmits the data to a receiving node at a first rate. If the data is not received error-free, the node is able to reduce the number of data bits of the current packet that are being transmitted and to increase the amount of redundant data. The node repeats the process until error-free transmission is obtained.

Abstract: A random-access local network having multiple nodes provides data communication across residential wiring such as telephone line as a network medium, where each node accesses the network medium using discrete multi-tone (DMT) modulated symbols. The effects of amplitude and phase distortion of transmitted DMT symbols are overcome, without the necessity of complex equalizers, by differentially encoding data prior to transmission, and recovering the transmitted data by comparing phase differentials between consecutive symbol tones. Each transmitted symbol is composed of a plurality of tone signals, each tone signal modulated according to a constellation point in a complex domain. A transmitter in a first node transmits a training symbol onto a network medium, where the DMT tones of the training symbol have an equal predetermined amount of energy.

Abstract: A physical layer device (PHY) device in a home LAN employs discrete multitone technology (DMT). The DMT system enables usage of existing residential wiring, which typically is telephone system grade twisted copper pair. The PHY device comprises a spectral image selection circuit to increase frequency diversity by examining all the images captured by a filter and restoring the transmitted signal based upon an image that may not be associated with the carrier frequency but its harmonics. Alternatively, the PHY device adjusts the sampling rate of its digital to analog convertor and accordingly filters to achieve desired grouping of spectral images.