Abstract: One embodiment of the present invention provides a method for the deposition of a Carbon containing layer on a Silicon surface wherein a (i) substantially Silicon-oxide-free or reduced oxide interface results between Silicon and the Carbon containing layer during the deposition. In another embodiment, the present invention provides a method for deposition of a Carbon containing layer wherein the deposition process is substantially soot (particle)-free or reduction of soot.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: A process for silanizing carbon nanotubes, wherein the carbon nanotubes are oxidized and subsequently exposed to a saturated gas phase including one or more organosilane derivatives which form covalent bonds to the carbon nanotubes with siloxane formation.

Abstract: A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric material.

Abstract: A process for silanizing carbon nanotubes, wherein the carbon nanotubes are oxidized and subsequently exposed to a saturated gas phase including one or more organosilane derivatives which form covalent bonds to the carbon nanotubes with siloxane formation.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.

Abstract: A method for forming self-aligned air-gaps as IMD wherein the interconnect lines are covered with self-aligned capping layer and wherein the process of forming the capping layer is a maskless process is provided.

Abstract: One embodiment of the present invention provides a method for the deposition of a Carbon containing layer on a Silicon surface wherein a (i) substantially Silicon-oxide-free or reduced oxide interface results between Silicon and the Carbon containing layer during the deposition. In another embodiment, the present invention provides a method for deposition of a Carbon containing layer wherein the deposition process is substantially soot (particle)-free or reduction of soot.

Abstract: A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

Abstract: A structured, elastic stamp device is disclosed for producing the physical contact of the reactant with the substrate. More specifically, the device comprises a stamp device for carrying out soft-lithographic processes which comprises a base, which is produced from a polymer material, and at least one structured stamp surface of the base, which has a definable surface relief, the stamp surface being structured by means of an impression of a master element which has a defined primary surface relief.

Abstract: A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.

Abstract: Process for contact-connection of carbon nanotubes as part of their integration in an electric circuit, wherein the nanotubes, after they have been applied to metallic interconnects of the electric circuit, are connected to the interconnects at contact locations by electroless metallization.

Abstract: A process for the selective and areal deposition of a catalyst is disclosed, which is intended for the growth of nanotubes, on an interconnect line in an integrated circuit or chip. The process includes providing an acidic or alkaline aqueous solution of the catalyst; applying the solution to the interconnect line; and removing the excess solution.

Abstract: A method for targeted deposition of a nanotube on a planar surface includes providing a ram made from elastomeric material and having a relief structure on its surface. A microfluid capillary system, with an inlet and an outlet, is then formed by applying the ram to a planar substrate. A dispersion of nanotubes is brought into contact with the inlet, thereby enabling capillary force to disperse the nanotubes. through the microfluid capillary system. The resulting dispersion of nanotubes is then dried and the ram removed.

Abstract: The invention relates to a process for producing a nanoelement arrangement and to a nanoelement arrangement. In the process for producing a nanoelement arrangement, a first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material.

Abstract: A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.

Abstract: A method of inferring the existence of light by means of a measurement of the electrical characteristics of a nanotube bound to a dye first of all involves bringing a nanotube derivatized with a dye into contact with two conductor tracks. An electrical parameter of the nanotube is then measured via the two conductor tracks without exposure to light. Then the dye bound to the nanotube is irradiated, and the electrical parameter of the nanotube is then measured via the two conductor tracks with exposure to light. The difference between the value of the electrical parameter measured without exposure to light and the corresponding parameter measured with exposure to light is then established. Finally it is inferred, as a function of the difference established, whether light is present.

Abstract: In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al2O3 is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al2O3 in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Abstract: The present invention relates to a method for the targeted deposition of nanotubes, in particular carbon nanotubes, on planar surfaces by exploiting capillary forces using microfluid capillary systems.