Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

Abstract: A method of forming a pattern includes providing a structure having an etch mask layer disposed over a pattern layer disposed over a dielectric layer. Disposing first and second trench plugs having different material compositions in the etch mask layer, the first and second trench plugs overlaying gamma and beta block mask portions respectively of the pattern layer. Forming an array of self-aligned spacers disposed on sidewalls of mandrels, the spacers and mandrels defining alternating beta and gamma regions extending normally to the dielectric layer, the gamma region and beta regions extending though portions of the first and second trench plug respectively. Selectively etching the structure to remove any portion of the first trench plug within the beta region and any portion of the second trench plug within the gamma region. Selectively etching the structure to form a pattern in the pattern layer including the block mask portions.

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.

Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.

Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.

Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.

Abstract: A document processing method for a medical office includes receiving, at a server with a network interface, electronic documents from a medical office. The server includes a software application adapted to recognize an expected class of electronic documents corresponding to the medical office. The method also includes processing the electronic documents received from the medical office to extract data therefrom based on a recognition that the electronic documents belong to the expected class of electronic documents corresponding to the medical office. The method also includes automatically mapping the extracted data from the processed electronic documents to a data repository on the server. The data repository is accessible by the medical office through the network interface.

Abstract: A document processing method includes receiving, at a server with a network interface, electronic documents from a user. The server includes a software application adapted to recognize a class of electronic documents to which the electronic documents belong. The method also includes processing the electronic documents received from the user to extract data therefrom based on a recognition that the electronic documents belong to the class of electronic documents. The extracted data corresponds to a service being provided to the user. The method also includes automatically mapping the extracted data from the processed electronic documents to a data repository on the server. The data repository is accessible by the user through the network interface. The method also includes electronically generating output data based on the mapped data from the data repository to the user. The output data corresponds to the service being provided to the user.

Abstract: A method according to the present disclosure includes receiving information, including a user-desired destination as an end location, from a user-operated computing device and electronically determining a current location of a user as a beginning location based on positional information received at the user-operated computing device. The method also includes electronically generating potential routes from the beginning location to the end location based on the information and electronically selecting one of the potential routes as a selected route. The method also includes outputting, to the user-operated computing device, the electronically selected route. The selected route includes one or more of a mass transit portion, a motor vehicle route portion, and a pedestrian walking route portion. The method also includes outputting, to the user-operated computing device, navigation instructions based on a then-current location of the user between the beginning location and the end location.

Abstract: A document processing method includes receiving, at a server with a network interface, electronic documents from a user. The server includes a software application adapted to recognize a class of electronic documents to which the electronic documents belong. The method also includes processing the electronic documents received from the user to extract data therefrom based on a recognition that the electronic documents belong to the class of electronic documents. The extracted data corresponds to a service being provided to the user. The method also includes automatically mapping the extracted data from the processed electronic documents to a data repository on the server. The data repository is accessible by the user through the network interface. The method also includes electronically generating output data based on the mapped data from the data repository to the user. The output data corresponds to the service being provided to the user.

Abstract: A document processing method for a medical office includes receiving, at a server with a network interface, electronic documents from a medical office. The server includes a software application adapted to recognize an expected class of electronic documents corresponding to the medical office. The method also includes processing the electronic documents received from the medical office to extract data therefrom based on a recognition that the electronic documents belong to the expected class of electronic documents corresponding to the medical office. The method also includes automatically mapping the extracted data from the processed electronic documents to a data repository on the server. The data repository is accessible by the medical office through the network interface.