Patents by Inventor Eugene Anikin
Eugene Anikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10552565Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: GrantFiled: November 22, 2016Date of Patent: February 4, 2020Assignee: Mentor Graphics CorporationInventors: Eugene Anikin, Fedor G. Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman
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Publication number: 20170147732Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: ApplicationFiled: November 22, 2016Publication date: May 25, 2017Applicant: Mentor Graphics CorporationInventors: Eugene Anikin, Fedor G. Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman
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Patent number: 9652574Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: GrantFiled: April 25, 2011Date of Patent: May 16, 2017Assignee: Mentor Graphics CorporationInventors: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman
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Patent number: 9507902Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: GrantFiled: April 25, 2011Date of Patent: November 29, 2016Assignee: Mentor Graphics CorporationInventors: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman
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Publication number: 20110289471Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: ApplicationFiled: April 25, 2011Publication date: November 24, 2011Inventors: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman
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Publication number: 20090077506Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.Type: ApplicationFiled: May 15, 2008Publication date: March 19, 2009Inventors: Eugene Anikin, Fedor Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman
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Publication number: 20080034332Abstract: Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout design for the layer then is divided into separate areas or “windows,” and a target density for each window is determined. More particularly, each window is analyzed to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. In some implementations, the target density will be the smallest density that will comply with each of the specified density value constraints. Once the target density for the window has been determined, the fill polygons required to most closely approach this target density are selected and added to the circuit layout design.Type: ApplicationFiled: May 1, 2007Publication date: February 7, 2008Applicant: Mentor Graphics CorporationInventors: Eugene Anikin, Fedor Pikus, John Stedman, Laurence Grodd, David Abercrombie