Abstract: A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a first output of the first inverter and a second input coupled to a second output of the first inverter, wherein the first and second outputs of the first inverter are separated by a resistor, and having an output coupled to the bus hold input node.

Abstract: A dynamic clamp 200 selectively clamps overshoot on a signal line 100 when overshoot is likely, while not clamping the received signal at times when overshoot is not likely encountered. A Driver Disable signal 102 disables the output of an output driver 110 so that it presents a high impedance to the signal line 100. An activation element 310 asserts a Clamp Enable signal 311, for example, in response to a transition of the received signal that occurs, for example, during a period in which a corresponding Driver Disable signal 102 is asserted. A deactivation element 320 asserts a Clamp Disable signal 321, for example, a predetermined deactivation delay period after the Clamp Enable signal 311 is asserted. A clamping portion 330 selectively clamps the received signal 100 beginning with the assertion of the Clamp Enable signal and ending with the assertion of the Clamp Disable signal.

Abstract: An output circuit having undershoot/overshoot reduction, and improved propagation delay. A damping control circuit branch is provided, including a resistor and a diode connected in parallel between a first node and a second node, the second node being coupled to an output node. An output transistor, having a gate, is coupled by its source and drain between a power supply and the second node. A predriver circuit is adapted to receive an input signal and provide a voltage at the gate.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: An input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition stabilizer circuit includes a resistor having a first terminal connected to the input of the input circuit;, and a capacitor. A first MOS device is connected by a source and a drain between a second terminal of the resistor and a first terminal of the capacitor, while a second MOS device is connected by a source and a drain between a second terminal of the capacitor and ground. A delay circuit is adapted to provide a signal to a gate of the first MOS device and a gate of the second MOS device corresponding to a signal at the input of the input circuit, but delayed by a first predetermined interval. In some embodiments the delay circuit is provided in two parts, with the signal provided to the first MOS device being delayed by a further amount, as compared with the signal provided to the second MOS device.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: An improved pre-driver circuit 33, which uses only three additional components to bypass the back-gate current blocking diodes for increased circuit speed during normal operation, while reducing the Ioff current and satisfying over-voltage tolerant specification. This unique circuit uses the pre-driver's tri-state input signal to control the pull-up path of the pre-driver circuit's upper output (UOP) transistor 3010.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: An improved pre-driver circuit 33, which uses only three additional components to bypass the back-gate current blocking diodes for increased circuit speed during normal operation, while reducing the Ioff current and satisfying over-voltage tolerant specification. This unique circuit uses the pre-driver's tri-state input signal to control the pull-up path of the pre-driver circuit's upper output (UOP) transistor 3010.

Abstract: One aspect of the invention is an integrated circuit (10,110) comprising a digital circuit operable to generate a first signal (21,111) and a driver circuit (20 and 30, 120 and 130) coupled to the signal generating circuit (21,111) and to an output load (40, 140). The driver circuit (20 and 30, 120 and 130) comprises a first transistor (MDA,MODA) operable to sink a first amount of current from an output node (38, 138) when activated and a second transistor (MDC,MODC) operable to sink a second amount of current from the output node (38, 138) when activated. The driver circuit (20 and 30, 120 and 130) also comprises a third transistor (MP1, MP4) coupled to the first transistor (MDA,MODA) and operable to activate the first transistor (MDA,MODA) and the second transistor (MDC,MODC) in response to a transition of a first signal.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.