Patents by Inventor Eugene B. Hogenauer
Eugene B. Hogenauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10817184Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: GrantFiled: January 22, 2019Date of Patent: October 27, 2020Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20190155518Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 10185502Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: GrantFiled: May 25, 2017Date of Patent: January 22, 2019Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20170262193Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 9665397Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.Type: GrantFiled: July 15, 2014Date of Patent: May 30, 2017Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8949576Abstract: An apparatus for processing operations in an adaptive computing environment is provided. The adaptive computing environment including at least one processing node. A node includes a memory configured to receive and store data. The data is received from a programmable interconnection network and stored. The node also includes an execution unit configured to perform a signal processing operation. The operation is performed using data retrieved from the memory and an output result is generated. The output result may be used for further computations or sent directly to the programmable interconnection network for transfer to another processing node in the adaptive computing environment.Type: GrantFiled: February 13, 2003Date of Patent: February 3, 2015Assignee: NVIDIA CorporationInventor: Eugene B. Hogenauer
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Publication number: 20140331231Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8782196Abstract: A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.Type: GrantFiled: June 11, 2012Date of Patent: July 15, 2014Assignee: Sviral, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20130117404Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: ApplicationFiled: June 11, 2012Publication date: May 9, 2013Applicant: Sviral, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8406281Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: GrantFiled: October 28, 2009Date of Patent: March 26, 2013Assignee: QST Holdings LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Patent number: 8200799Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: GrantFiled: February 9, 2009Date of Patent: June 12, 2012Assignee: QST Holdings LLCInventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20100220706Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: October 28, 2009Publication date: September 2, 2010Inventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20100037029Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: ApplicationFiled: February 9, 2009Publication date: February 11, 2010Applicant: QST HOLDINGS LLCInventors: W. James SCHEUERMANN, Eugene B. HOGENAUER
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Patent number: 7653710Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: GrantFiled: May 21, 2003Date of Patent: January 26, 2010Assignee: QST Holdings, LLC.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 7620097Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: GrantFiled: December 23, 2008Date of Patent: November 17, 2009Assignee: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20090104930Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20090103594Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Method and system for implementing a system acquisition function for use with a communication device
Publication number: 20080247443Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: June 18, 2008Publication date: October 9, 2008Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann -
Method and system for implementing a system acquisition function for use with a communication device
Patent number: 7400668Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences-the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: GrantFiled: February 4, 2002Date of Patent: July 15, 2008Assignee: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann -
Patent number: 7225279Abstract: A data distributor in a computational unit of an integrated circuit is enclosed. The data distributor receives data from a network and distributes the data to a plurality of components within the computational unit. The data distributor includes an input mechanism for receiving the data from the network, and distributes the data to a selected component of the plurality of components, a control mechanism responsive to a control signal for distributing the data to the selected component using a data distribution selected between a look-up table-based memory write and a point-to-point distribution with acknowledgement. The plurality of components comprises a Peek/Poke Module, an Execution Unit, a DMA Engine, and a Hardware Task Manager Message Generator. The selected data distribution type may comprise using an output port number or a direct-memory address transfer or an interrupt to distribute the data.Type: GrantFiled: May 21, 2003Date of Patent: May 29, 2007Assignee: NVIDIA CorporationInventors: W. James Scheuermann, Eugene B. Hogenauer