Patents by Inventor Eugene Bullock

Eugene Bullock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070267632
    Abstract: Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 M? while at the same time allowing a sufficient degree of localization to be obtained for root cause failure analysis. The detection of resistances lower than 1 M? nominally requires a probe current greater than 1 micro ampere for detection on an electron beam inspection system.
    Type: Application
    Filed: January 3, 2007
    Publication date: November 22, 2007
    Inventor: Eugene Bullock
  • Publication number: 20060134810
    Abstract: A method for electrically testing a wafer that includes: receiving a wafer having a first layer that is at least partly conductive and a second layer formed over the first layer, following production of openings in the second layer; directing towards the wafer a first set of beams of charged particles that are oriented at a first set of angles in relation to the wafer, whereas each angel of the first set of angles deviates substantially from normal, so as to pre-charge an area of the second layer without substantially pre-charging the first layer; scanning the area of the wafer by a second set of beams of charged particles that are oriented at a second set of angles in relation to the wafer, and collecting charged particles scattered from the area wafer.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventor: Eugene Bullock
  • Publication number: 20060054816
    Abstract: System and a method for electrically testing a semiconductor wafer, the method including: (a) scanning a charged particle beam along at least one scan line while maintaining an electrode located at a vicinity of the wafer at a first voltage that differs from a voltage level of a first scanned portion of the wafer, and collecting charged particles scattered from the first scanned portion; (b) scanning a charged particle beam along at least one other scan line while maintaining the electrode at a second voltage that differs from a voltage level of a second scanned portion such as to control a charging state of at least an area that comprises the first and second scanned portions; and (c) repeating the scanning stages until a predefined section of the wafer is scanned.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 16, 2006
    Inventor: Eugene Bullock