Patents by Inventor Eugene Cloud
Eugene Cloud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080111574Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: January 21, 2008Publication date: May 15, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070103167Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: May 10, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075722Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075723Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075725Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Patent number: 7149361Abstract: A method and apparatus for image processing to detect changes in a scene includes compressing by computing a wavelet transform of an image corresponding to the scene, thresholding coefficients associated with the transform, and comparing a subset of coefficients with values to detect and indicate a change in the image. Values such as averages and a standard deviation therefrom can be generated during training by processing N training images. Determining whether a change has occurred includes determining the value of image sets, standard deviation and training sets, and comparing these, based on the type of change to be ascertained, to statistical information.Type: GrantFiled: November 26, 2002Date of Patent: December 12, 2006Assignee: Lockheed Martin CorporationInventors: Larry Peele, Eugene Cloud
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Publication number: 20060201705Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.Type: ApplicationFiled: May 12, 2006Publication date: September 14, 2006Inventors: Akram Salman, Warren Farnworth, Alan Wood, J. Brooks, Eugene Cloud
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Publication number: 20060192582Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: April 24, 2006Publication date: August 31, 2006Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20060131702Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.Type: ApplicationFiled: January 26, 2006Publication date: June 22, 2006Inventors: Leonard Forbes, Eugene Cloud, Kie Ahn
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Publication number: 20060128059Abstract: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.Type: ApplicationFiled: February 1, 2006Publication date: June 15, 2006Inventors: Kie Ahn, Leonard Forbes, Eugene Cloud
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Publication number: 20060124981Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.Type: ApplicationFiled: February 6, 2006Publication date: June 15, 2006Inventors: Leonard Forbes, Eugene Cloud, Wendell Noble
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Publication number: 20060115929Abstract: A method for assembling semiconductor dice includes orienting at least one second semiconductor die with the active surface thereof facing the active surface of a first semiconductor die. A structure on an active surface of one of the semiconductor dice may interact with a peripheral edge or other feature of another of the semiconductor dice to facilitate alignment of corresponding bond pads of the semiconductor dice. Corresponding bond pads of the first and at least one second semiconductor dice are connected. For example, conductive structures may be formed or placed between the corresponding bond pads. Bond pads of the first semiconductor die that are laterally beyond an outer periphery of each second semiconductor die may be electrically connected to corresponding contacts.Type: ApplicationFiled: January 4, 2006Publication date: June 1, 2006Inventors: Eugene Cloud, Paul Farrar
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Publication number: 20050093566Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 10, 2004Publication date: May 5, 2005Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20040101200Abstract: A method and apparatus for image processing to detect changes in a scene includes compressing by computing a wavelet transform of an image corresponding to the scene, thresholding coefficients associated with the transform, and comparing a subset of coefficients with values to detect and indicate a change in the image. Values such as averages and a standard deviation therefrom can be generated during training by processing N training images. Determining whether a change has occurred includes determining the value of image sets, standard deviation and training sets, and comparing these, based on the type of change to be ascertained, to statistical information.Type: ApplicationFiled: November 26, 2002Publication date: May 27, 2004Inventors: Larry Peele, Eugene Cloud
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Patent number: 6210993Abstract: A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.Type: GrantFiled: July 6, 1999Date of Patent: April 3, 2001Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood, Mike Brooks, Eugene Cloud
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Patent number: 5990566Abstract: A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.Type: GrantFiled: May 20, 1998Date of Patent: November 23, 1999Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood, Mike Brooks, Eugene Cloud