Abstract: An electrostatic discharge (ESD) protection circuit for integrated circuitry having a switching ground bus for isolating switching noise includes an ESD protection bus. A first transistor pair includes a PNP transistor and an NPN transistor, with each of the transistors having an emitter connected to a signal input/output pad. A second transistor pair has a PNP transistor and an NPN transistor having emitters connected to the switching ground bus. For each of the PNP transistors, the base is connected to the ESD protection bus and the collector is connected to a "clean" ground bus. For each of the NPN transistors, a base is connected to the clean ground bus and a collector is connected to the ESD protection bus. In this configuration, the PNP of one transistor pair and the NPN of the other transistor pair are able to operate as a distributed silicon controlled rectifier to protect a drive transistor during an ESD event. Optionally, a switching V.sub.

Abstract: Electrostatic discharge (ESD) protection circuitry having a string of diode-connected field-effect transistors (FETs) connected between a bus and ground plane for triggering a shunt element, such as a large n-channel FET, connected between the same or a different bus and the ground plane. The bus or buses are diode-connected through the base-emitter junction of pnp transistors to signal pads, as well as to a positive voltage power supply. The string of FETs turns on when the pad-to-ground voltage, and thus the bus-to-ground voltage, exceeds a threshold characteristic of an ESD event. The string acts as a voltage divider to bring a node between two of the FETs up to a voltage that will activate an n-channel trigger FET, which is part of a resistive-load inverter. This drives another inverter that in turn drives the shunt FET. When the voltage is pulled back down below the threshold voltage, the shunt FET continues to shunt current to the ground plane for the duration of the ESD event.