Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: A CCD imaging system is provided, including a short focal length lens for accepting light from the scene to be imaged and a charge storage medium having a charge storage substrate that is curved in a selected nonplanar focal surface profile and located a selected distance from the lens with the focal surface facing the lens, the focal surface profile and the lens-to-substrate distance selected such that the light accepted by the lens is in focus at the position of the substrate. There is provided a support substrate on which the nonplanar charge storage substrate is supported to maintain the selected surface profile of the charge storage substrate.

Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: A CCD imaging system is provided, including a short focal length lens for accepting light from the scene to be imaged and a charge storage medium having a charge storage substrate that is curved in a selected nonplanar focal surface profile and located a selected distance from the lens with the focal surface facing the lens, the focal surface profile and lens-to-substrate distance selected such that the light accepted by the lens is in focus at the position of the substrate. There is provided a support substrate on which the nonplanar charge storage substrate is supported to maintain the selected surface profile of the charge storage substrate.

Abstract: The wafer thickness of a CCD front illuminated silicon wafer is reduced to about ten to twenty microns, the Al substrate is removed and a 5-35 nanometer silicon oxide layer is produced on the thinned back of the silicon wafer followed by implanting boron ions within the back surface to a depth up to about ten nanometers. Furnace annealing the wafer is now carried out, and the Al substrate is redeposited to enable the formation of gate contacts.

Abstract: An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B.

Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract: A charge modulation device having a semiconductor region of a first conductivity type. An epitaxial layer of second conductivity type is provided on a portion of the semiconductor region so as to define an FET channel region. A first epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET drain region, the first epitaxial region being electrically isolated from the semiconductor region. A second epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET source region, the second epitaxial region being electrically isolated from the semiconductor region. A third epitaxial region of the first conductivity type or a metal oxide semiconductor is provided to the channel region between the source and drain regions.

Abstract: A charge-coupled device having an array of pixel elements formed in a substrate, which device is operable in a first state to expand the depletion well regions of each pixel element into the substrate for storing incoming photoelectrons therein and in a second state to contract the expanded depletion well regions to prevent storage of photoelectrons in the contracted depletion well regions.

Abstract: Charge integration is selectively interrupted in a semiconductor imager with thinned substrate, by modulating the electric field normal to its back-illuminated surface. This suppresses smear generated during field transfer in certain types of imager when exposed to high-energy images, for example. The thinned substrate is cemented with an electrically insulating epoxy to a glass backing plate bearing a transparent electrode, the potential on which is varied to modulate the drift field.

Abstract: Significant reductions in transfer smear for charge sweep device imagers is made possible by performing the charge sweep operation during only the line retrace period of the operating cycle of the imager. Complete elimination of transfer smear is then possible by using an optical means for blocking the imager from incident illumination during said line retrace periods.

Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.

Abstract: Back-illuminated CCD imagers of interline transfer type are made possible by deep, highly doped implant regions which bury the CCDs with respect to the back-illuminated surfaces of the imager substrates. Transfer smear caused by photoconversion in the CCD charge transfer channels must be suppressed in certain of these back-illuminated CCD imagers of interline transfer type, and suitable suppression methods are described.

Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.

Abstract: A CCD imager of field transfer type having an image register statically clocked during image integration in a number of phases greater than it is dynamically clocked with during field transfer to a field storage register, when the image register and the field storage register are clocked in synchronous phase with each other.

Abstract: An imaging device includes a wafer of single crystal semiconductor material having a first surface with an input surfacing region which extends into the wafer from the first surface and a second surface with a charge storage portion which includes a plurality of discrete charge storing regions which extend into the wafer of the second surface. The wafer includes a potential barrier within the input signal sensing portion for controlling blooming. The wafer is improved by including a passivation region within the input sensing portion for stabilizing the energy level of the conductivity band of the minority carriers at the Fermi energy level of the semiconductor wafer. Additionally, an electrical leakage reduction region extends into the wafer from the second surface. The leakage reduction region is contiguous with each of the discrete charge storage regions.

Abstract: Field-rate flicker is suppressed in a CCD imager having a three-phase operated image register provided interlacing by integrating odd-numbered fields with only the first clock phase high and even-numbered fields with only the second and third clock phases high. The flicker is suppressed by making the gate electrodes in the A register receiving the second and third clock phases of equal lengths, half that of the gate electrodes receiving the first clock phase.

Abstract: A target for vidicons and image intensifier tubes include a potential barrier less than about 1500 A from an input signal sensing surface. The targets also include various passivation means for stabilizing the energy level configuration along the input signal sensing surface by substantially fixing the valence or conduction band along that surface relative to the Fermi level.