Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract: Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.

Abstract: A system and method for exposing and/or milling a copper metallization layer disposed in dielectric that may have an overlying polyimide layer preferably by use of a FIB machine system used for exposing/milling aluminum metallization layers is disclosed. The method includes using a gas assisted (GAS) system for exposing a portion of a copper metal trace disposed in a dielectric and includes the step of removing a portion of the dielectric overlying the portion of the metal trace using the GAS system activated with a dielectric selective chemical that does not have a significant spontaneous (non ion-beam induced) reaction with the metal trace. The system includes a focused ion beam (FIB) machine for exposing/milling a portion of a metal trace disposed in a dielectric substrate wherein the metal trace is copper.

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract: An improved process is provided for forming a multilayer structure (18) suitable for tape automated bonding thereto or for forming contacts. In the process, a first layer (12) of aluminum is formed on a substrate (10), a second layer (14) of a TiW alloy is formed on the first layer of aluminum, and a third layer (16) of gold is formed on the second layer of the TiW alloy, to which third layer of gold bonding is done. The improvement comprises annealing the second layer of the TiW alloy in an inert atmosphere at a temperature less than about 500.degree. C. for a period of time sufficient to form a film of an Al--TiW phase (20), believed to comprise TiAl.sub.3, at the interface between the first layer of aluminum and the second layer of the TiW alloy. The annealing is done prior to forming the third layer of gold on the second layer of the TiW alloy.