Abstract: A planar semiconductor integrated circuit chip structure comprising a surface from which a plurality of regions of different conductivity types extend into the chip to provide the transistors and resistors wherein said transistors and resistors are arranged in a plurality of repetitive cells, each of said cells containing a sufficient number of transistors and resistors to form a selected type of logic circuit. The cells are arranged in an orthogonal array with the cells in substantially parallel rows in both orthogonal directions. The structure includes a level of metallization disposed above and insulated from the array by at least one layer of electrically insulative material. This level of metallization comprises a plurality of groups of substantially parallel lines respectively disposed above and running parallel to a corresponding plurality of interfaces between rows of said cells in one of the orthogonal directions.