Abstract: A method of fabricating a unit cell of a focal plane array includes providing an integrated circuit substrate, depositing a proximal portion of a dielectric layer on the substrate, and etching a plurality of recess structures into the dielectric layer. Each of the plurality of recess structures defines a partial via and includes sidewalls that extend from the first surface to a bottom portion of the respective recess structure. The method also includes forming a capacitor structure, depositing a distal portion of the dielectric layer on the capacitor structure and a region of the proximal portion of the dielectric layer, forming a plurality of vias passing to the capacitor structure, forming a metal layer, and forming a detector overlying the metal layer. The plurality of vias are positioned between the capacitor structure and the metal layer and electrically connect the capacitor structure to the metal layer.

Abstract: A photodetector structure includes a readout integrated circuit (ROIC) substrate and a dielectric layer overlaying the IC substrate. The dielectric layer defines a plurality of recesses formed in a top surface of the dielectric layer where each recess has at least one sidewall that extends from a top surface of the dielectric layer to a bottom portion of each respective recess. A capacitor structure forms a portion of the photodetector structure and includes a first electrode formed across the top surface of the dielectric layer and across the at least one sidewall of each recess of the plurality of recesses. A capacitor dielectric layer is formed across the first electrode and a second electrode is formed across the capacitor dielectric layer. A detector overlays the capacitor structure.

Abstract: A photodetector structure includes a readout integrated circuit (ROIC) substrate and a dielectric layer overlaying the IC substrate. The dielectric layer defines a plurality of recesses formed in a top surface of the dielectric layer where each recess has at least one sidewall that extends from a top surface of the dielectric layer to a bottom portion of each respective recess. A capacitor structure forms a portion of the photodetector structure and includes a first electrode formed across the top surface of the dielectric layer and across the at least one sidewall of each recess of the plurality of recesses. A capacitor dielectric layer is formed across the first electrode and a second electrode is formed across the capacitor dielectric layer. A detector overlays the capacitor structure.

Abstract: Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.

Abstract: Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.

Abstract: Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.