Patents by Inventor Eugene F. Rice

Eugene F. Rice has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7155130
    Abstract: A driver, e.g., for use with electro-optic (E/O) modulators. The driver is configured to generate a driving signal based on an electronic NRZ input data signal and an input clock signal. The driver converts the NRZ input data signal to an RZ format and produces an amplified RZ signal that can be applied to an E/O modulator. The amplification gain of the driver is adjustable to enable interfacing with different modulators. In one embodiment of the invention, the driving signal is generated based on a comparison between the NRZ input data signal and an offset clock signal generated from the input clock signal. The width of pulses in the driving signal, e.g., corresponding to logical “ones,” may be tuned by, e.g., changing the DC offset of the clock signal. The driver may be implemented as an ASIC configured to operate at the data rate of, e.g., 10 GBit/s.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: December 26, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Yves L. Baeyens, Young-Kai Chen, Wei-Chiao W. Fang, Andreas Leven, Eugene F. Rice
  • Publication number: 20040223765
    Abstract: A driver, e.g., for use with electro-optic (E/O) modulators. The driver is configured to generate a driving signal based on an electronic NRZ input data signal and an input clock signal. The driver converts the NRZ input data signal to an RZ format and produces an amplified RZ signal that can be applied to an E/O modulator. The amplification gain of the driver is adjustable to enable interfacing with different modulators. In one embodiment of the invention, the driving signal is generated based on a comparison between the NRZ input data signal and an offset clock signal generated from the input clock signal. The width of pulses in the driving signal, e.g., corresponding to logical “ones,” may be tuned by, e.g., changing the DC offset of the clock signal. The driver may be implemented as an ASIC configured to operate at the data rate of, e.g., 10 GBit/s.
    Type: Application
    Filed: February 28, 2002
    Publication date: November 11, 2004
    Inventors: Yves L. Baeyens, Young-Kai Chen, Wei-Chiao W. Fang, Andreas Leven, Eugene F. Rice