Abstract: Multicast packets that are received on a port of a network device and forwarded to multiple output ports are stored in memory and respective primary control entries which define them are converted to secondary control entries defining multiple unicast packets before a scheduling algorithm is applied. The packets are reconstituted after the application of the scheduling algorithm has been applied to the control entries. For VPLS packets that are received on a single port and replicated multiple times on one or more output ports, a replication database may be used in conjunction with a replication engine to convert the control entry for a received packet into multiple control entries defining unicast packets for each of the destination ports before the scheduling algorithm is applied. This method is applicable to the replication of packets onto a Virtual Private LAN.

Abstract: Multicast packets that are received on a port of a network device and forwarded to multiple output ports are stored in memory and respective primary control entries which define them are converted to secondary control entries defining multiple unicast packets before a scheduling algorithm is applied. The packets are reconstituted after the application of the scheduling algorithm has been applied to the control entries. For VPLS packets that are received on a single port and replicated multiple times on one or more output ports, a replication database may be used in conjunction with a replication engine to convert the control entry for a received packet into multiple control entries defining unicast packets for each of the destination ports before the scheduling algorithm is applied. This method is applicable to the replication of packets onto a Virtual Private LAN.

Abstract: A direct memory access controller (DMAC) is provided to transfer bytes from arbitrary offset byte boundaries while performing data check operations in parallel to the movement of data in parallel through the DMA controller. The DMA controller moves data during each memory cycle and validates the moved data at the destination memory during the writing of bytes to the destination address.

Abstract: A digital glitch filter includes first and second NOR gates coupled with feedback to form a first sampling stage, third and fourth NOR gates coupled to the output of the first and second NOR gate, respectively, and fifth and sixth NOR gates coupled with feedback to form a second sampling stage and coupled to the output of the third and fourth NOR gate, respectively, as well as three AND gates. A clock pulse generator is used to generate the pulse signals required by the glitch filter. For multiple-signal applications, the glitch filter requires relatively few gates.