Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: A heterogeneous processor architecture is described.

Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.

Abstract: Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.

Abstract: Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

Abstract: Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.

Abstract: Examples are disclosed for aggregating compute, memory and input/output (I/O) resources across devices. In some examples, a first device may migrate to a second device at least some compute, memory or I/O resources associated with executing one or more applications. Migration of at least some compute, memory or I/O resources for executing the one or more applications may enable the first device to save power and/or utilize enhanced processing capabilities of the second device. In some examples, migration of compute, memory or I/O resources for executing the one or more applications may occur in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: Improved enhanced TV programming provides the capability for a TV viewer watching one channel to be notified of interesting programming events happening or about to happen on other channels. The present invention overcomes the problem addressed by “surfing TV channels” by providing notifications that alert enhanced TV viewers to other programming events happening or about to happen on different channels that are not presently being watched. This enables the viewer to watch a primary program on one channel without interruption and be timely notified about interesting programming events about to occur on other channels. The viewer then may have the option of switching to another channel based on the information included with the event notification.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract: A heterogeneous processor architecture is described.

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.