Abstract: High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.

Abstract: High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.

Abstract: A signal parameter estimator includes curve fitting of multiple ideal spectral shapes.

Abstract: A signal parameter estimator includes curve fitting of multiple ideal spectral shapes.

Abstract: An adaptive scaling processor operates in combination with a conventional automatic gain control controller providing an amplification gain A to m-ary symbol-modulated communication signals, the scaling processor scaling by a scaling factor Z the m-ary communication signal for providing an over all gain of an (A)(Z) product minimizing the BER that is optimum for the communications channel for improved BER performance in communication systems.

Abstract: An adaptive scaling processor operates in combination with a conventional automatic gain control controller providing an amplification gain A to m-ary symbol-modulated communication signals, the scaling processor scaling by a scaling factor Z the m-ary communication signal for providing an over all gain of an (A)(Z) product minimizing the BER that is optimum for the communications channel for improved BER performance in communication systems.

Abstract: A multithreaded processor is programmed for executing multiple simultaneous working programs by respective processor worker threads each executing the identical code having identical results for achieving redundant operations that can be compared to each other by one or more checker threads for determining when one of the working programs or checker threads has failed for a single event fault detection and recovery of a failed worker or checker monitoring program so as to mitigate the effects of single event failure that may be due to radiation.

Abstract: A multithreaded processor is programmed for executing multiple simultaneous working programs by respective processor worker threads each executing the identical code having identical results for achieving redundant operations that can be compared to each other by one or more checker threads for determining when one of the working programs or checker threads has failed for a single event fault detection and recovery of a failed worker or checker monitoring program so as to mitigate the effects of single event failure that may be due to radiation.

Abstract: Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or “force-rebalance,” of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

Abstract: Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or “force-rebalance,” of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.