Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

Abstract: An assembly includes a first semiconductor die with bond pads arranged in an array on an active surface thereof and at least one second semiconductor die with bond pads on an active surface thereof flip-chip connected to bond pads of the first semiconductor device. The at least one second semiconductor die is oriented with the active surface thereof facing the active surface of the first semiconductor die. Corresponding bond pads of the first and at least one second semiconductor dice are connected by placing or forming conductive structures therebetween. A package includes the assembly and a carrier. The first semiconductor die of the assembly is oriented over the carrier with the active surface of the first semiconductor die facing the carrier. Bond pads of the first semiconductor die located laterally beyond an outer periphery of each second semiconductor die are electrically connected to corresponding contacts by way of conductive structures.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.