Abstract: Initialization data is received by a memory multiplexer (MEMMUX) and stored in a plurality of registers of the MEMMUX without reading data from memory. The storage of the initialization data in the MEMMUX registers may be sequential or simultaneous. The initialization data is then written to memory along with error detection and correction data as desired.

Abstract: A burst error scrubbing system and method consecutively detects and corrects errors in all of memory, beginning with data stored at the first address of memory and continuing until data stored at the last address of memory is read, corrected and written back to memory. Burst error scrubbing is not performed during a refresh cycle but instead is programmable so that the burst scrubbing can be performed at a specific time interval.

Abstract: A method and system for automatic configuration of memory devices having a same initial address. Initially, all of the memory devices in the computer system are disabled but one enabled memory device. An initial address of the enabled memory device is changed to a new unique address. Then, unless all of the memory devices have been enabled, one previously disabled memory device is enabled to produce a next enabled memory device having the initial address. The steps of changing the initial address of the enabled memory device to a new unique address and enabling a next enabled memory device having the initial address are then repeated until the initial address of each of the memory devices has been changed to a new unique address.

Abstract: A system including a number of circuit boards is provided that configures itself automatically. Any number of circuit boards can be placed in any order including sandwich arrangements where the circuit boards automatically configure themselves without any manual intervention by a skilled individual changing jumpers or strapping devices. The multi-board system removes the possibility of an error occurring while configuring the memory and registers.

Abstract: A device has a plurality of memory portions, a first portion having an output enable and input/output connections and a second portion without output enables and having separate input and output connections. A tri-state buffer has its input coupled to the output connection of the second memory portion and its output coupled to the input connection of the second memory portion. A control connection of the buffer is coupled to the output enable of the device.

Abstract: Two or more memory arrays are coupled to two or more error detection and correction (EDAC). Each memory array has a plurality of memory devices each having a plurality of outputs. The outputs of each memory are divided among the EDACs such that no more than two outputs from a single memory device are coupled to a single EDAC.

Abstract: A concurrent arbitration system and method are provided wherein the most recent requester retains control of a system resource under certain conditions and is allowed access to the resource during a portion of an arbitration cycle which will result in the granting of access to the resource by another requester. This overlapping of a resource access cycle and an arbitration cycle decreases the overall arbitration time and therefore reduces the overall resource access time.

Abstract: A programmable logic device having four AND gate means defined therein is used to combine first and second inputs as well as multiplexing and latch signals. These signals are ANDed together (first input and multiplexing signals; inverted multiplexing signal and latch signal and second input; inverted multiplexing signal, second input signal and device output signal; and inverted latch signal and device output signal) to provide four output signals which are ORed together to produce the device output signal.