Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.

Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Abstract: Various embodiments of the present disclosure are directed towards an optoelectronic device. The device includes a substrate, and a germanium photodiode region extending into an upper surface of the substrate. The germanium photodiode region has a curved upper surface that extends past the upper surface of the substrate. A silicon cap overlies the curved upper surface of the germanium photodiode region. There is an absence of oxide between the curved upper surface of the germanium photodiode region and an upper surface of the silicon cap.

Abstract: The present disclosure relates an integrated chip structure. The integrated chip structure includes a base substrate having one or more interior surfaces defining a recess within an upper surface of the base substrate. An epitaxial material is disposed within the recess. A first doped photodiode region is disposed within the epitaxial material and has a first doping type. A second doped photodiode region is disposed within the epitaxial material and has a second doping type. The second doped photodiode region laterally surrounds the first doped photodiode region. A doped epitaxial layer is disposed horizontally and vertically between the base substrate and the epitaxial material. The doped epitaxial layer has the second doping type.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region disposed in a semiconductor substrate and a second doped region disposed in the semiconductor substrate. A photodetector is disposed between the first doped region and the second doped region. The photodetector has a lower surface that arcs between opposing sidewalls of the photodetector in a cross-sectional view. The first doped region and the second doped region contact the lower surface of the photodetector.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: Various embodiments of the present disclosure are directed towards an optoelectronic device. The device includes a substrate, and a germanium photodiode region extending into an upper surface of the substrate. The germanium photodiode region has a curved upper surface that extends past the upper surface of the substrate. A silicon cap overlies the curved upper surface of the germanium photodiode region. There is an absence of oxide between the curved upper surface of the germanium photodiode region and an upper surface of the silicon cap.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.