Patents by Inventor Eugene Jinglun Tam

Eugene Jinglun Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200364547
    Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.
    Type: Application
    Filed: April 17, 2020
    Publication date: November 19, 2020
    Applicants: ICLEAGUE Technology Co., Ltd., AP Memory Technology Corp.
    Inventors: Wenliang CHEN, Eugene Jinglun TAM, Lin MA, Joseph Zhifeng XIE, Alessandro MINZONI
  • Patent number: 10103133
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 16, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Eugene Jinglun Tam
  • Publication number: 20170323875
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Application
    Filed: July 25, 2017
    Publication date: November 9, 2017
    Inventor: Eugene Jinglun TAM
  • Publication number: 20170323876
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Application
    Filed: July 25, 2017
    Publication date: November 9, 2017
    Inventor: Eugene Jinglun TAM
  • Patent number: 9728526
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Eugene Jinglun Tam
  • Patent number: 9703702
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 11, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Eugene Jinglun Tam
  • Patent number: 9324389
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 26, 2016
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Patent number: 9305651
    Abstract: An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 5, 2016
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20160086668
    Abstract: An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventor: Eugene Jinglun Tam
  • Patent number: 9275706
    Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 1, 2016
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Patent number: 9165683
    Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: October 20, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Patent number: 9104591
    Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 11, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Patent number: 9098428
    Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 4, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20150178197
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20150085575
    Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20140359200
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20140355325
    Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Publication number: 20140241082
    Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam
  • Patent number: 8780639
    Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: July 15, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
  • Publication number: 20140164879
    Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventor: Eugene Jinglun Tam