Abstract: A write drive logic circuit is described. The write driver logic circuit comprises a set of write drivers, with each one of the set of write drivers having an input and an output, such that each write driver is responsive to an input signal applied to the input to provide a write output signal at the output as a function of the input signal. A set of memory devices (e.g. shift registers) is provided, one for each write driver. Each one of the shift registers stores unique head identification information and includes an output to controllably output a signal representative of the unique head identification information. Furthermore, each one of a set of multiplexers includes an output, a first input coupled to a corresponding one of the outputs of the set of shift registers to receive the signal representative of the unique identification information stored in the respective shift register and a second input coupled to a common write data line that transmits a signal representative of preselected information.

Abstract: A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.

Abstract: There is shown and described a high speed bus architecture which uses a common control bus and permits high speed data transfer between a plurality of active and/or passive users while reducing the system overhead structure which was previously required.