Abstract: A clock generator circuit for producing with very little power dissipation an output clock signal having levels determined by positive and negative power supply levels from an input clock signal having levels determined by the positive power supply level and ground. In a low state of the input clock signal, an upper or first transistor of an output transistor pair connected in series between positive and negative power supply levels is turned off by applying a ground level to the base thereof, while the lower or second transistor of the output transistor pair is turned off by applying a positive potential to its base. When the input clock signal makes a transition from the low state to the high state, a bootstrap capacitor is charged between the positive and negative power supply levels to provide a boosted positive voltage to turn on the upper transistor. While the bootstrap capacitor is charging, the base of the lower transistor is lightly grounded to partially turn it on.

Abstract: Disclosed is a field effect transistor multivibrator for generating a controlled pulse width waveform. The generated waveform has fast rise and fall times and a pulse width linearly controlled by the capacitor in one of the cross-coupling paths. An input signal is applied to a first inverter which provides its output to a cross coupled pair of transistors. The first of the cross coupled transistors has its gate electrode coupled directly to the drain electrode of the second transistor which in turn is connected to the output terminal. The cross coupling path from the drain of the first transistor to the gate of the second cross coupled transistor includes a capacitor and a grounded gate depletion mode field effect transistor as well as an additional transistor providing a connection between the capacitor and ground potential.

Abstract: Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages.