Abstract: A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: An image comprising a plurality of pixels at a predetermined pixel pitch, is received, A plurality of image intensity signals, are received at readout circuitry responsive to an image intensity per pixel. A portion of the received image is divided into a plurality of fixed paxels, each paxel comprising a rectilinear collection of pixels, having a first length and first predetermined number of rows, and second width having second predetermined number of columns. The plurality of fixed paxels are provided to a respective plurality of configurable Analog to Digital Converters (ADCs) responsive to a respective plurality of paxels and configurable to generate respective ADC output signals that implement a tradeoff between Effective Number of Bits (ENoB) and power consumption while maintaining a substantially fixed spatial frequency. Some paxels corresponding to a first predetermined fixation point are digitized with higher ENoB than the other paxels. A foveated image is generated.

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a sigma-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: A sigma delta modulator (SDM) data converter system is provided. The SDM data converter system comprises a signal path, a feedback signal path, and a multi-bit quantizer disposed in a feedforward path. The signal path receives an input signal to be processed. The feedback signal path provides a feedback signal that is subtracted from the input signal. The multi-bit quantizer is disposed in the feedforward path so as to receive the input signal after the feedback signal has been subtracted from it. Te multi-bit quantizer uses feedforward dynamic element matching (DEM) to spectrally shape mismatch errors in the SDM data conversion system and produce an output signal, wherein the output signal of the multi-bit quantizer is used for at least a portion of the feedback signal.

Abstract: A hearing aid (5) has a &Sgr;&Dgr; delta modulator (26) that receives an input data stream (18) and produces a &Sgr;&Dgr; modulated output data stream, having three states {+1,0,−1}. An H-bridge (28) receives the &Sgr;&Dgr; modulated output data stream and produces an output signal for delivery to an associated acoustic transducer (24). A circuit (30) is provided between the &Sgr;&Dgr; modulator (26) and the H-bridge (28) to force the &Sgr;&Dgr; modulated data stream to return to a zero state as part of each non-zero output period in the &Sgr;&Dgr; modulated data stream. A differential oscillator (34) having a differential oscillator output signal clocks a differential latch (32) to provide a differentially latched output to the H-bridge (28).

Abstract: A method and apparatus of correlated double sampling is disclosed by creating sampled and clamped signals from CCD imager outputs that are in phase with the CCD imager outputs comprising: providing an image sensor having an analog output; sensing the output of the image sensor via system electronics; identifying and extracting portions of a reset signal within the analog output signal; and modifying existing clocks in response to extracted portions of the reset signal.

Abstract: A method and apparatus of correlated double sampling is disclosed by creating sampled and clamped signals from CCD imager outputs that are in phase with the CCD imager outputs comprising: providing an image sensor having an analog output; sensing the output of the image sensor via system electronics; identifying and extracting portions of a reset signal within the analog output signal; and modifying existing clocks in response to extracted portions of the reset signal.

Abstract: An imaging device for generating an image signal includes an image sensing device for producing an image signal subject to one or more clock signals and a circuit for generating one or more of the clock signals, wherein the clock signal generating circuit is responsive to a programmable input signal for adjusting a duty cycle of at least one of the clock signals. In particular, by clocking two recirculating shift registers out of phase and parallel loading them with a programmable bit pattern to produce the output clock signals, the frequency of an input clock that is required to produce the output clock signals can be reduced by half.

Abstract: A method and apparatus for automatic lateral alignment of front and rear images in a two sided scanning system. A line store is used for each camera to capture image data from a calibration target. A control processor then uses this image data to compute offset values which get stored for future use. The offset is then loaded into a hardware cropping circuit to correct the camera alignment in real time. Difficult manual alignment procedures are thus eliminated.

Abstract: This invention relates to an apparatus for converting a grayscale image to a bitonal image which provides improved tonal rendition with minimal loss of resolution. The invention attenuates the low spatial frequency component of the digital image and uses a similarly attenuated thresholder to convert the image to a bitonal image. When used with a dither type thresholder, this technique allows for simultaneous "continuous tone" and "line art" thresholding with minimal circuit complexity.

Abstract: This invention relates to a method for converting a grayscale image to a bitonal image which provides improved tonal rendition with minimal loss of resolution. The invention attenuates the low spatial frequency component of the digital image and uses a similarly attenuated thresholder to convert the image to a bitonal image. When used with a dither type thresholder, this technique allows for simultaneous "continuous tone" and "line art" thresholding with minimal circuit complexity.