Patents by Inventor Eugene Nogavich

Eugene Nogavich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5049974
    Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture of such components are presented. The interconnect device has two layers of circuitry, one for signal transmission and one for voltage plane. The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power or ground) plane layers.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: September 17, 1991
    Assignee: Roger Corporation
    Inventors: Gregory H. Nelson, Sanford Lebow, Eugene Nogavich
  • Patent number: 4995941
    Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture thereof are presented. The interconnect device has two layers of circuitry, one for signal transmission and one for voltage plane. The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power or ground) plane layers.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: February 26, 1991
    Assignee: Rogers Corporation
    Inventors: Gregory H. Nelson, Sanford Lebow, Eugene Nogavich
  • Patent number: 4159222
    Abstract: The method of manufacturing printed circuitry with sufficiently high resolution to permit line densities of at least 1 mil lines on 3 mil centers includes the steps of placing a thickness of dry film photoresist on a smooth, polished substrate or carrier optionally, applying a thin lubricating layer of spray wax to the exposed surface of the photoresist, wringing a mask defining a desired conductive circuit pattern into high integrity, intimate contact with the surface of the resist, exposing and developing the resist to remove the resist from the smooth surface in regions where the conductive circuit pattern is to be formed, electroplating the conductors within the voids formed in the resist; removing all remaining resist, laminating a flowable dielectric material to the smooth surface of the substrate and the conductive circuit pattern, and removing the laminate material and conductive circuit pattern from the smooth surface.
    Type: Grant
    Filed: January 11, 1977
    Date of Patent: June 26, 1979
    Assignee: Pactel Corporation
    Inventors: Sanford Lebow, Daniel Nogavich, Eugene Nogavich