Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. The voter circuit provides an output feedback frequency signal based upon a majority vote of the sub-divide by N functions.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A method and latch circuit are provided for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices. A latch circuit includes critical data and clock paths and non-critical sections. A low voltage threshold (LVT) transistor is used only in the critical data and clock paths. The non-critical sections are implemented with regular VT, (RVT), or low leakage (LLD) transistors. The latch circuit advantageously is implemented using LVT devices in the internal critical paths of the latch and RVT output buffer transistors.

Abstract: A data storage element for use in LSSD compliant circuit designs. The data storage element has an alternate, or scan, data input circuit that has increased immunity to electrical noise while maintaining lower power consumption than the circuits used for primary data input. This increased noise immunity reduces the probably that noise on the alternate data input will cause an unintended change of data state stored in the data storage element. Modification of latch circuits used in the data storage element allow a reduction in the number of transistors used in the latch circuits, thereby compensating for the increase in transistors used in the alternate data input circuit and allowing the data storage element to use the same number of transistors as prior designs that have less noise immunity on their alternate data inputs.

Abstract: A delay element for use in circuit designs. The delay element accepts an input signal, typically a clock signal, and provides a delay of that signal to adjust path timing such as is used for the clocking of imbedded arrays of integrated circuits. By using uniform channel length devices, the delay element provides enhanced tuning and tracking of device parameters of the timing circuit as well as simplifying modeling of the delay element circuit.