Patents by Inventor Eugene O'Sullivan
Eugene O'Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10840441Abstract: Techniques for MRAM patterning using a diamond-like carbon hardmask are provided. In one aspect, a method of forming an MRAM device includes: forming an MRAM stack on a substrate; depositing a metal hardmask layer on the MRAM stack; depositing a diamond-like carbon layer on the metal hardmask layer; forming a patterned resist on the diamond-like carbon layer; patterning the diamond-like carbon layer using the patterned resist to form a diamond-like carbon pillar; patterning the metal hardmask layer using the diamond-like carbon pillar to form a patterned metal hardmask; and patterning the MRAM stack into an MRAM pillar using the patterned metal hardmask to form the MRAM device. An MRAM device is also provided.Type: GrantFiled: September 14, 2018Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Anthony Annunziata, Nathan P. Marchack, Eugene O'Sullivan, Chandrasekharan Kothandaraman
-
Publication number: 20200091418Abstract: Techniques for MRAM patterning using a diamond-like carbon hardmask are provided. In one aspect, a method of forming an MRAM device includes: forming an MRAM stack on a substrate; depositing a metal hardmask layer on the MRAM stack; depositing a diamond-like carbon layer on the metal hardmask layer; forming a patterned resist on the diamond-like carbon layer; patterning the diamond-like carbon layer using the patterned resist to form a diamond-like carbon pillar; patterning the metal hardmask layer using the diamond-like carbon pillar to form a patterned metal hardmask; and patterning the MRAM stack into an MRAM pillar using the patterned metal hardmask to form the MRAM device. An MRAM device is also provided.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Inventors: Anthony Annunziata, Nathan P. Marchack, Eugene O'Sullivan, Chandrasekharan Kothandaraman
-
Patent number: 10276439Abstract: After bonding a second substrate to a first substrate through a bonded material layer to provide a bonded structure, through dielectric via (TDV) openings of different depths are concurrently formed in the bonded structure by performing a single anisotropic etch using fluorine-deficient species that are obtained by dissociation of fluorocarbon-containing molecules.Type: GrantFiled: June 2, 2017Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Sebastian U. Engelmann, Li-Wen Hung, Eric Joseph, Eugene O'Sullivan, Jeff Waksman, Cornelia Tsang Yang
-
Publication number: 20180350677Abstract: After bonding a second substrate to a first substrate through a bonded material layer to provide a bonded structure, through dielectric via (TDV) openings of different depths are concurrently formed in the bonded structure by performing a single anisotropic etch using fluorine-deficient species that are obtained by dissociation of fluorocarbon-containing molecules.Type: ApplicationFiled: June 2, 2017Publication date: December 6, 2018Inventors: Sebastian U. Engelmann, Li-Wen Hung, Eric Joseph, Eugene O'Sullivan, Jeff Waksman, Cornelia Tsang Yang
-
Patent number: 9839570Abstract: A motorized walker of the present invention is includes a first section and a second section including a pair of front legs and rear legs and handle members. Each rear leg and front leg include respective extension elements telescopingly engaged with the terminal ends of the respective rear legs and the front legs to allow a user to adjust the height of the walker. Each section includes a front wheel and a motor. Each section and the rear leg present a wheel of different construction.Type: GrantFiled: July 16, 2015Date of Patent: December 12, 2017Inventor: Eugene O'Sullivan
-
Publication number: 20170014298Abstract: A motorized walker of the present invention is includes a first section and a second section including a pair of front legs and rear legs and handle members. Each rear leg and front leg include respective extension elements telescopingly engaged with the terminal ends of the respective rear legs and the front legs to allow a user to adjust the height of the walker. Each section includes a front wheel and a motor. Each section and the rear leg present a wheel of different construction.Type: ApplicationFiled: July 16, 2015Publication date: January 19, 2017Inventor: Eugene O'Sullivan
-
Publication number: 20130327652Abstract: Plating bath solutions and methods for depositing selenium generally include an aqueous plating bath containing a soluble selenium source and a soluble surfactant additive, wherein the soluble surfactant additive is selected from the group consisting of an alkane sulfonic acid, an alkane phosphonic acid and mixtures thereof, wherein the alkane group defining the alkane sulfonic acid and the alkane phosphonic acid has less than 25 carbon atoms The method includes immersing a conductive substrate to be plated into the aqueous plating bath; and electroplating selenium onto the substrate to form a continuous and particle free film.Type: ApplicationFiled: June 7, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EUGENE O'SULLIVAN, LUBOMYR T. ROMANKIW, NAIGANG WANG
-
Publication number: 20130327651Abstract: Plating bath solutions and methods for depositing selenium generally include an aqueous plating bath containing a soluble selenium source and a soluble surfactant additive, wherein the soluble surfactant additive is selected from the group consisting of an alkane sulfonic acid, an alkane phosphonic acid and mixtures thereof, wherein the alkane group defining the alkane sulfonic acid and the alkane phosphonic acid has less than 25 carbon atoms The method includes immersing a conductive substrate to be plated into the aqueous plating bath; and electroplating selenium onto the substrate to form a continuous and particle free film.Type: ApplicationFiled: June 14, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EUGENE O'SULLIVAN, LUBOMYR T. ROMANKIW, NAIGANG WANG
-
Patent number: 8174332Abstract: A phase lock loop pre-charging system and method are described. In one embodiment, a phase lock loop pre-charge system includes a bias component for generating a pre-charge voltage, and an activation component for activating the bias component. In one exemplary implementation the pre-charge voltage is utilized to facilitate pre-charging of a phase lock loop voltage controlled oscillator. In one embodiment, the bias component includes replica bias components that track the voltage controlled oscillation control voltage over varying process, voltage and temperature characteristics. The phase lock loop pre-charging systems and methods can be utilized to reduce lock time for a circuit.Type: GrantFiled: December 17, 2009Date of Patent: May 8, 2012Assignee: Cypress Semiconductor CorporationInventors: Carel J. Lombaard, Eugene O'Sullivan, Paul Walsh
-
Patent number: 7859240Abstract: A circuit and method are provided for interrupting current flow into a voltage regulator from an output thereof when a voltage source (Vpwr) drops below an output voltage (Vout). In one embodiment, the circuit comprises: (i) a comparator supplied by Vout including an output and inputs coupled to Vpwr and Vout; and (ii) transistors coupled to and controlled by the comparator, including a first transistor configured to interrupt a first current path extending between Vout and Vpwr through an output-leg of the regulator when Vpwr drops below Vout. Preferably, the regulator includes a reference-leg and a feedback-circuit coupling Vout thereto, and the first transistor also interrupts a second current path between Vout and Vpwr through the feedback-circuit and reference leg. More preferably, the reference-leg comprises resistors through which it is coupled to ground, and the transistors include a second transistor to interrupt a third current path between Vout and ground.Type: GrantFiled: January 22, 2008Date of Patent: December 28, 2010Assignee: Cypress Semiconductor CorporationInventors: Lionel Geynet, Eugene O'Sullivan
-
Patent number: 7728675Abstract: A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.Type: GrantFiled: March 29, 2007Date of Patent: June 1, 2010Assignee: Cypress Semiconductor CorporationInventors: Ian Kennedy, Eugene O'Sullivan, Carel J. Lombaard
-
Patent number: 7636019Abstract: A phase lock loop pre-charging system and method are described. In one embodiment, a phase lock loop pre-charge system includes a bias component for generating a pre-charge voltage, and an activation component for activating the bias component. In one exemplary implementation the pre-charge voltage is utilized to facilitate pre-charging of a phase lock loop voltage controlled oscillator. In one embodiment, the bias component includes replica bias components that track the voltage controlled oscillation control voltage over varying process, voltage and temperature characteristics. The phase lock loop pre-charging systems and methods can be utilized to reduce lock time for a circuit.Type: GrantFiled: June 2, 2006Date of Patent: December 22, 2009Assignee: Cypress Semiconductor CorporationInventors: Carel J. Lombaard, Eugene O'Sullivan, Paul Walsh
-
Patent number: 7368299Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.Type: GrantFiled: July 14, 2004Date of Patent: May 6, 2008Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Gill Yong Lee, Eugene O'Sullivan
-
Publication number: 20070020934Abstract: Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.Type: ApplicationFiled: July 8, 2005Publication date: January 25, 2007Applicant: International Business Machines CorporationInventors: Michael Gaidis, Sivananda Kanakasabapathy, Eugene O'Sullivan
-
Publication number: 20070012656Abstract: An etching process is employed to selectively pattern the exposed magnetic film layer of a magnetic thin film structure. The magnetic structure to be etched includes at least one bottom magnetic film layer and at least one top film layer which are separated by a tunnel barrier. The etching process employs various etching steps that selectively remove various layers of the magnetic thin film structure stopping on the tunnel barrier layer.Type: ApplicationFiled: June 8, 2005Publication date: January 18, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eugene O'Sullivan, David Abraham
-
Publication number: 20060289381Abstract: An etching process is employed to selectively pattern the top magnetic film layer, the tunnel barrier, and the pinned bottom magnetic layer of a magnetic thin film structure. The pinned bottom magnetic film layer has an antiferromagnetic layer or a Ru spacer formed thereunder. The etching process employs various etching steps that selectively remove various layers of the magnetic thin film structure stopping on the antiferromagnetic layer or the Ru spacer. The progress of this etching process can be monitored by measuring the electrochemical potential difference of a part or wafer containing a magnetic structure with respect to a reference electrode simultaneously with the selective etching process.Type: ApplicationFiled: June 8, 2005Publication date: December 28, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eugene O'Sullivan, Daniel Worledge
-
Publication number: 20060105676Abstract: A signal processing system has the detected mechanical, chemical, optical, electrical, or thermal signals generated during chemical-mechanical polishing (CMP) process collected, analyzed and differentiated with respect to time in-situ, in order to reveal the different stages during CMP for process control and end-pointing purposes. This control and/or end-pointing scheme may be used to detect the interface between two material layers sharing similar properties such as those of low-k dielectric stacks for semiconductor applications.Type: ApplicationFiled: November 17, 2004Publication date: May 18, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eugene O'Sullivan, Shom Ponoth, Wei-Tsu Tseng
-
Publication number: 20060014305Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.Type: ApplicationFiled: July 14, 2004Publication date: January 19, 2006Inventors: Gill Lee, Eugene O'Sullivan
-
Publication number: 20050079647Abstract: A method (and resulting structure) of patterning a magnetic thin film, includes using a chemical transformation of a portion of the magnetic thin film to transform the portion to be non-magnetic and electrically insulating.Type: ApplicationFiled: October 8, 2003Publication date: April 14, 2005Applicant: International Business Machines CorporationInventors: David Abraham, Eugene O'Sullivan
-
Patent number: 6812141Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.Type: GrantFiled: July 1, 2003Date of Patent: November 2, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Michael C. Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O'Sullivan, Gregory Costrini, Stephen L. Brown, Frank Findeis, Chanro Park