Abstract: Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.

Abstract: Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.

Abstract: Systems and methods of writing data to a buffer during a buffer cycle are described. The buffer has a plurality of buffer banks having various fill levels. The buffer determines a first portion of banks from the plurality of buffer banks. The first portion of banks unfilled banks. A rank can be assigned to each of the first portion of banks and a candidate set of banks chosen from the first portion of banks. A target bank is then chosen from the candidate set and the data is written to that bank. The ranking may be random. Furthermore, the target bank can be chosen based on ranking, fill level, or both.

Abstract: Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.

Abstract: Systems and methods of writing data to a buffer during a buffer cycle are described. The buffer has a plurality of buffer banks having various fill levels. The buffer determines a first portion of banks from the plurality of buffer banks. The first portion of banks unfilled banks. A rank can be assigned to each of the first portion of banks and a candidate set of banks chosen from the first portion of banks. A target bank is then chosen from the candidate set and the data is written to that bank. The ranking may be random. Furthermore, the target bank can be chosen based on ranking, fill level, or both.

Abstract: Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Abstract: A network device for processing packets includes at least one ingress module for performing switching functions on a packet, a memory management unit for storing the packet and at least one egress module for transmitting the packet to at least one port. The at least one egress module is configured to maintain multiple queues for the at least one port, including a purge queue, and to store the packet in the purge queue when an error condition is determined when the end of the packet is received by the at least one ingress module.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one ingress module is configured to determine a priority for the incoming data, where that priority is mapped to a discrete number of priority groups and where the priority groups are determined on a per-port basis and provide guaranteed delivery or best throughput, and flow of data through the network device is controlled on a basis of at least one of the priority groups and assigned priorities.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one ingress module is configured to determine a priority for the incoming data, where that priority is mapped to a discrete number of priority groups and where the priority groups are determined on a per-port basis and provide guaranteed delivery or best throughput, and flow of data through the network device is controlled on a basis of at least one of the priority groups and assigned priorities.

Abstract: A network device for processing packets includes at least one ingress module for performing switching functions on a packet, a memory management unit for storing the packet and at least one egress module for transmitting the packet to at least one port. The at least one egress module is configured to maintain multiple queues for the at least one port, including a purge queue, and to store the packet in the purge queue when an error condition is determined when the end of the packet is received by the at least one ingress module.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Abstract: A service aware flow control apparatus and method for multiple classes of data packets. A flow control sender includes a buffer of an ingress port per Class Group or Class of Service (COS). A counter per COS tracks an amount of buffer utilization per ingress port per COS, and each counter comprises an XOFF threshold level of congestion and an XON threshold. A controller detects, during transmission of the data packets, a counter associated with a buffer for a particular COS has risen to be greater than or equal to the XOFF threshold level of congestion. A flow control receiver ceases transmission of the data packets to the buffer for the particular COS experiencing congestion and allowing transmission of the data packets corresponding to other COS in the flow control sender.

Abstract: A dynamic threshold apparatus and method are provided including a flow control sender and a flow control receiver. The flow control sender includes an ingress port with one or more Class Groups (CG) defined including a shared buffer pool, a shared counter per ingress port per CG tracking an amount of the shared buffer pool utilized by each CG, an ingress port utilization counter per ingress port tracking an amount of the shared buffer pool utilized by the ingress port, and a controller computing a dynamic threshold for each CG, comparing the dynamic threshold of each CG with the ingress port utilization counter, and determining a particular CG experiencing congestion when the ingress port utilization counter is greater than the dynamic threshold for the particular CG. The flow control receiver ceases transmission of data packets to the particular CG experiencing congestion and allows transmission of the data packets corresponding to other CGs.