Abstract: An apparatus may comprise a power management system. Other embodiments are described and claimed.

Abstract: An arrangement is provided for modeling the performance of a communication network. One or two sigmoid functions may be used to model the performance of a physical layer versus the SINR of a transmission channel across all of the available modulation and coding schemes. The sigmoid function(s) abstract(s) away all of the available modulation and coding choices to provide an estimate for the PHY throughput. This estimate can then be utilized by higher network layers to obtain the network throughput at the application level, which may then be used to produce a data stream by an application source. Based on the data stream thus produced, the quality of information to be transmitted via a channel, when received, may be estimated.

Abstract: An apparatus may comprise a power management system. Other embodiments are described and claimed.

Abstract: A system, apparatus, method, and article including a control module to manage transmission of packets in a channel of a wireless network. The control module to receive real-time information about the channel. The control module to adapt transmission of said packets based on the information. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: Digital signals are sent in a predetermined sequence from one end of a bus wire and are received at the other end. Each of the digital signals of the received sequence is compared with a corresponding predetermined signal of the predetermined sequence to determine whether an error has occurred. Data obtained concerning bus errors may be used to handle bus errors during runtime.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: A power control circuit and corresponding technique for reducing power consumption by an electronic device and thereby increasing performance. The power control circuit comprises a controller, a clock generation circuit and a power supply circuit. The controller detects whether a condition exists to scale the voltage and frequency of the electronic device and in response, signals the clock generation circuit to perform frequency scaling on the electronic device and the power supply circuit to perform voltage scaling on the electronic device. The condition may include a situation where the temperature of the electronic device is detected to have exceeded a thermal band. The condition may also include a situation where the electronic device is detected to be idle for a selected percentage of its run time.

Abstract: A mechanism and means for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. The present invention includes a method and mechanism for indicating to the functional unit whether it is required for use. The present invention also includes a method and mechanism for powering down the functional unit transparent and independent of the rest of the functional units when the functional unit is not required for use.

Abstract: A computer system that contains devices and peripherals that have power management capabilities incorporated therein that are responsible for placing the computer system in a reduced power consumption state. A controller monitors bus cycles from a processor. Upon the completion of each bus cycle, the controller provides a completion indication to the processor. In the present invention, the controller withholds the completion indication for a period of time after completion of each of the selected bus cycles to control power consumption by the processor, thereby extending the time in which the processor is in the reduced power consumption state. In this way, power consumption in the processor is controlled within an instruction boundary.

Abstract: A computer system having switchable 3.3 volt or 5 volt interface bus. The computer system includes a microprocessor and multiple peripheral integrated circuits. The microprocessor and other peripheral integrated circuits are coupled to the interface bus through groups of buffers on the integrated circuits. These buffers operate at the voltage level of the interface bus and include voltage translation circuitry for translating interface bus signals to voltage level at which the core logic of the microprocessor and other peripheral chips operate.

Abstract: A mechanism for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. A method and mechanism for indicating to the functional unit whether it is required for use. Also included is a method and mechanism for powering down the functional unit transparent and independent of the rest of the functional units when the functional unit is not required for use.

Abstract: A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register.