Abstract: A decoder system comprises a tensor-product code (TPC) decoder that decodes a received data stream to generate a decoded signal. A mark module that replaces low-density parity check (LDPC) parity bits of the decoded signal with 0s to generate a reset output signal. A deinterleave module deinterleaves error correction parity bits that are within the reset output signal to generate a deinterleaved signal that comprises a decoded portion and a concatenated portion. The concatenated portion comprises the error correction parity bits. A parity decoder module removes the concatenated portion from the deinterleaved signal.

Abstract: A low-density parity check (LDPC) decoder comprises a decoded data stream generator that generates a decoded data stream based on a received data stream and a set of matrix-based codewords. The matrix-based codewords form a LDPC parity check matrix H. A decoder control module at least one of prewrites or replaces a selected portion of at least one of the plurality of codewords with zeros prior to generation of the decoded data stream.

Abstract: A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check matrix H and is associated with a current decoding iteration. A fourth memory comprises likelihood ratios. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration and the likelihood ratios.

Abstract: An encoder system includes a receive module that receives a data stream. A parity generation module generates parity bits based on the data stream and a tensor-product code. A parity insertion module combines the parity bits and the data stream to generate encoded bits.