Abstract: A switched capacitor (12) providing an effective resistance having a relatively long time constant. The switched capacitor (12) includes a technique for switching an input switch (14) associated with the capacitor (12) between a first input potential and a second input potential where the second input potential is proportional to the first input potential. In one specific implementation, the capacitor is a primary capacitor (30) having a three position input switch (46) that is switchable between a ground contact (48), an intermediate contact (42) and the input potential, and a three position output switch (50) that is switchable between a first ground contact (56), a second ground contact (54) and an output potential. A secondary capacitor (32) includes a two position input switch (34) that is switchable between the input voltage and a ground contact (38), and an output switch (40) that is switchable between a ground contact (44) and the intermediate contact (42).

Abstract: Disclosed is a generator and method for using the generator to negate offset voltages in operational amplifiers. The generator includes an operational amplifier (op amp) whose input stage includes a current source coupled to a differential pair of input devices. The physical characteristics of the devices are such that an intentional offset voltage greater than the normal op amp offset voltage is provided in the input stage. The output terminal of the generator op amp is connected to the substrate terminal of one of the input devices. The offset voltages of other op amps can be negated by interconnecting the substrate terminal of one device in each input differential pair to the output terminal of the generator op amp and creating an intentional offset voltage in the input differential pair of each op amp.

Abstract: An improved CMOS signal magnitude detector (SMD) for accurately quantifying the peak-to-peak magnitude of a received signal is disclosed. The SMD includes a precision gain amplifier, positive and negative peak detectors and a switched capacitive amplifier. The recited components are coupled to form a combination circuit arrangement which receives a differential signal and outputs a single ended signal which is compared with a reference signal to provide a control signal when the differential signal is of a sufficient peak to peak voltage magnitude. The control signal may be used to gate the differential signal and generate an output signal representative of received data.

Abstract: A precision gain circuit arrangement for amplifying analog type signals is fabricated on an integrated chip with digital devices in a CMOS process. The circuit arrangement includes a high gain operational amplifier with a series connected pair of FET devices setting a reference voltage (V.sub.ref) at the inverting input of the operational amplifier and a feedback circuit including a parallel connected pair of FET devices and a biasing FET for said pair set the gain of said circuit arrangement.

Abstract: A process insensitive reference voltage generator includes a first and second identical FET devices coupled in a parallel configuration with a first biasing network, of FET devices, interconnecting the substrate terminal of the first FET device to a first node formed between a positive voltage supply and ground potential. The control terminal is connected to a second node whose voltage potential is different from that of the first node. The substrate terminal of the second FET device is connected to the source terminal. The source terminals of both FET devices are connected to the respective input terminals of an operational amplifier whose output is connected to the control terminal of said second FET device.

Abstract: An improved on chip single ended integrated circuit receiver includes a first circuit arrangement for setting a first referenced voltage level for an incoming signal, a second circuit arrangement for generating a second referenced voltage level with hysteresis and a third circuit arrangement for correlating the incoming signal with the second referenced voltage level and outputting a signal representative of the incoming signal. The second circuit arrangement includes a four terminal MOS FET device whose substrate electrode is connected to an active node formed between a pair of MOS FET devices and controlled by the output signal from the third circuit arrangement.